Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 48

10 Fm

0.1 Fm

10 Fm 0.1 Fm

10 Fm

0.1 Fm

VREFP

VMID

VCAP

VREFN

392W

OPA2822

ADS1602

0.001 Fm

392W

OPA2822

0.001 Fm

392W

OPA2822

0.001 Fm

2.5V

AGND

2 1

REF

-V

2 1

REF

2 1-

( )

£ -

REF

2 1-

( )

ADS1602

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

Table 1. Maximum Allowable Clock Source Jitter

for Different Input Signal Frequencies and

Amplitude

INPUT SIGNAL

MAXIMUM MAXIMUM MAXIMUM ALLOWABLE

FREQUENCY AMPLITUDE CLOCK SOURCE JITTER

1MHz –2dB 3.8ps

1MHz –20dB 28ps

500kHz –2dB 7.6ps

500kHz –20dB 57ps

100kHz –2dB 38ps

100kHz –20dB 285ps

DATA FORMAT

The 16-bit output data are in binary two’s

complement format as shown in Table 2. When the

input is positive out-of-range, exceeding the positive

full-scale value of V

REF

, the output clips to all 7FFFh

and the OTR output goes high.

Likewise, when the input is negative out-of-range by

going below the negative full-scale value of –V

REF

the output clips to 8000h and the OTR output goes

high. The OTR remains high while the input signal is

Figure 45. Recommended Buffer Circuit When

out-of-range.

Using an External Reference

Table 2. Output Code versus Input Signal

INPUT SIGNAL (INP – IDEAL OUTPUT

CLOCK INPUT (CLK)

INN) CODE

(1)

OTR

The ADS1602 requires an external clock signal to be

≥ +V

REF

(> 0dB) 7FFFh 1

applied to the CLK input pin. The sampling of the

–V

REF

(0dB) 7FFFh 0

modulator is controlled by this clock signal. As with

any high-speed data converter, a high quality clock is

0001h 0

essential for optimum performance. Crystal clock

oscillators are the recommended CLK source; other

0 0000h 0

sources, such as frequency synthesizers, are usually

inadequate. Make sure to avoid excess ringing on the

FFFFh 0

CLK input; keeping the trace as short as possible

helps.

8000h 0

Measuring high-frequency, large amplitude signals

requires tight control of clock jitter. The uncertainty

during sampling of the input from clock jitter limits the

8000h 1

maximum achievable SNR. This effect becomes more

pronounced with higher frequency and larger

magnitude inputs. Fortunately, the ADS1602

(1) Excludes effects of noise, INL, offset, and gain errors.

oversampling topology reduces clock jitter sensitivity

over that of Nyquist rate converters such as pipeline

OUT-OF-RANGE INDICATION (OTR)

and successive approximation converters by a factor

If the output code exceeds the positive or negative

of √16.

full-scale, the out-of-range digital output OTR will go

In order to not limit the ADS1602 SNR performance,

high on the falling edge of SCLK. When the output

keep the jitter on the clock source below the values

code returns within the full-scale range, OTR returns

shown in Table 1. When measuring lower frequency

low on the falling edge of SCLK.

and lower amplitude inputs, more CLK jitter can be

tolerated. In determining the allowable clock source

jitter, select the worst-case input (highest frequency,

largest amplitude) that will be seen in the application.