Datasheet

DAISY_IN
DOUT
SCLK
MSB
t
DISCK2ST
MSB
21
3 n n+1 n+2
MSB
LSB
t
DISCK2HT
t
DOST
0
LSB
n+3
1
CS
CLK
DIN
DOUT
2 3
8 1 2 83
t
CSSC
t
DIST
t
DIHD
t
DOHD
t
CSH
t
DOST
t
SCLK
t
SPWH
t
SPWL
t
SDECODE
t
SCCS
Hi-Z
t
CSDOZ
t
CSDOD
Hi-Z
t
CLK
SCLK
ADS131E04
ADS131E06
ADS131E08
SBAS561A –JUNE 2012–REVISED APRIL 2013 www.ti.com
TIMING CHARACTERISTICS
NOTE: SPI settings are CPOL = 0 and CPHA = 1.
Figure 1. Serial Interface Timing
(1) n = Number of channels × resolution + 24 bits. Number of channels is 4, 6, or 8; resolution is 16-bit or 24-bit.
Figure 2. Daisy-Chain Interface Timing
Timing Requirements For Figure 1 and Figure 2
(1)
2.7 V ≤ DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.0 V
PARAMETER DESCRIPTION MIN MAX MIN MAX UNIT
t
CLK
Master clock period 444 588 444 588 ns
t
CSSC
CS low to first SCLK: setup time 6 17 ns
t
SCLK
SCLK period 50 66.6 ns
t
SPWH, L
SCLK pulse width, high and low 15 25 ns
t
DIST
DIN valid to SCLK falling edge: setup time 10 10 ns
t
DIHD
Valid DIN after SCLK falling edge: hold time 10 11 ns
t
DOHD
SCLK falling edge to invalid DOUT: hold time 10 10 ns
t
DOST
SCLK rising edge to DOUT valid: setup time 17 32 ns
t
CSH
CS high pulse 2 2 t
CLKs
t
CSDOD
CS low to DOUT driven 10 20 ns
t
SCCS
Eighth SCLK falling edge to CS high 4 4 t
CLKs
t
SDECODE
Command decode time 4 4 t
CLKs
t
CSDOZ
CS high to DOUT Hi-Z 10 20 ns
t
DISCK2ST
Valid DAISY_IN to SCLK rising edge: setup time 10 10 ns
t
DISCK2HT
Valid DAISY_IN after SCLK rising edge: hold time 10 10 ns
(1) Specifications apply from –40°C to +105°C, unless otherwise noted. Load on DOUT = 20 pF || 100 kΩ.
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