Datasheet

ADS131E04
ADS131E06
ADS131E08
SBAS561A –JUNE 2012–REVISED APRIL 2013 www.ti.com
CHnSET: Individual Channel Settings (n = 1 to 8)
Address = 05h to 0Ch
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PDn GAINn2 GAINn1 GAINn0 0 MUXn2 MUXn1 MUXn0
This register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer
section for details. CH[2:8]SET are similar to CH1SET, corresponding to the respective channels (refer to
Table 10).
Bit 7 PDn: Power-down (n = individual channel number)
This bit determines the channel power mode for the corresponding channel.
0 = Normal operation (default)
1 = Channel power-down
Bits[6:4] GAINn[2:0]: PGA gain (n = individual channel number)
These bits determine the PGA gain setting.
000 = Do not use
001 = 1 (default)
010 = 2
011 = Do not use
100 = 4
101 = 8
110 = 12
111 = Do not use
Bit 3 Must be set to '0'
Bits[2:0] MUXn[2:0]: Channel input (n = individual channel number)
These bits determine the channel input selection.
000 = Normal input (default)
001 = Input shorted (for offset or noise measurements)
010 = Do not use
011 = MVDD for supply measurement
100 = Temperature sensor
101 = Test signal
110 = Do not use
111 = Do not use
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