Datasheet

ADS131E04
ADS131E06
ADS131E08
SBAS561A –JUNE 2012–REVISED APRIL 2013 www.ti.com
CONFIG1: Configuration Register 1
Address = 01h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
1 DAISY_IN CLK_EN 1 0 DR2 DR1 DR0
This register configures each ADC channel sample rate.
Bit 7 Must be set to '1'
Bit 6 DAISY_IN: Daisy-chain and multiple read-back mode
This bit determines which mode is enabled.
0 = Daisy-chain mode (default)
1 = Multiple read-back mode
Bit 5 CLK_EN: CLK connection
(1)
This bit determines if the internal oscillator signal is connected to the CLK pin when the CLKSEL pin = 1.
0 = Oscillator clock output disabled (default)
1 = Oscillator clock output enabled
Bit 4 Must be set to '1'
Bit 3 Must be set to '0'
Bits[2:0] DR[2:0]: Output data rate
These bits determine the output data rate and resolution. See Table 11 for details.
Modulator clock f
MOD
= f
CLK
/ 2. Where f
MOD
= 1.024 MHz.
(1) Additional power is consumed when driving external devices.
Table 11. Data Rate Settings
DR{2:0] RESOLUTION DATA RATE (kSPS)
000 16-bit output 64
001 16-bit output 32 (default)
010 24-bit output 16
011 24-bit output 8
100 24-bit output 4
101 24-bit output 2
110 24-bit output 1
111 Do not use NA
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