Datasheet

1 9 17 25

SCLK

DIN OPCODE 1 OPCODE 2 REG DATA 1 REG DATA 2

DOUT

1 9 17 25

SCLK

DIN

OPCODE 1 OPCODE 2

DOUT

REG DATA REG DATA + 1

ADS131E04

ADS131E06

ADS131E08

SBAS561A –JUNE 2012–REVISED APRIL 2013

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RREG: Read From Register

This opcode reads register data. The Register Read command is a two-byte opcode followed by the register data

output. The first byte contains the command opcode and the register address. The second opcode byte specifies

the number of registers to read – 1.

First opcode byte: 001r rrrr, where r rrrr is the starting register address.

Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1.

The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 41. When

the device is in read data continuous mode, an SDATAC command must be issued before the RREG command

can be issued. The RREG command can be issued at any time. However, because this command is a multibyte

command, there are SCLK rate restrictions depending on how the SCLKs are issued. See the Serial Clock

(SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for the entire

command.

Figure 41. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register)

(OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001)

WREG: Write to Register

This opcode writes register data. The Register Write command is a two-byte opcode followed by the register data

input. The first byte contains the command opcode and the register address.

The second opcode byte specifies the number of registers to write – 1.

First opcode byte: 010r rrrr, where r rrrr is the starting register address.

Second opcode byte: 000n nnnn, where n nnnn is the number of registers to write – 1.

After the opcode bytes, the register data follows (in MSB-first format), as shown in Figure 42. The WREG

command can be issued at any time. However, because this command is a multibyte command, there are SCLK

rate restrictions depending on how the SCLKs are issued. See the Serial Clock (SCLK) subsection of the SPI

Interface section for more details. Note that CS must be low for the entire command.

Figure 42. WREG Command Example: Write Two Registers Starting from 00h (ID Register)

(OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001)

Product Folder Links: ADS131E04 ADS131E06 ADS131E08