Datasheet

Hi-Z
START
DRDY
CS
SCLK
DIN
DOUT
RDATA Opcode
Status Register + n-Channel Data (216 Bits)
RDATA Opcode
ADS131E04
ADS131E06
ADS131E08
www.ti.com SBAS561A –JUNE 2012–REVISED APRIL 2013
SDATAC: Stop Read Data Continuous
This opcode cancels the Read Data Continuous mode. There are no SCLK rate restrictions for this command,
but the following command must wait for 4 t
CLK
cycles to execute.
RDATA: Read Data
Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode).
There are no SCLK rate restrictions for this command, and there is no wait time needed for subsequent
commands or data retrieval SCLKs. To retrieve data from the device after the RDATA command is issued, make
sure either the START pin is high or the START command is issued. When reading data with the RDATA
command, the read operation can overlap the next DRDY occurrence without data corruption. Figure 40 shows
the recommended way to use the RDATA command. RDATA is best suited for systems where register settings
must be read or changed often between conversion cycles.
Figure 40. RDATA Usage
Sending Multibyte Commands
The ADS131E0x serial interface decodes commands in bytes and requires 4 t
CLK
cycles to decode and execute.
Therefore, when sending multibyte commands, a 4-t
CLK
period must separate the end of one byte (or opcode)
and the next.
Assuming SCLK is 2.048 MHz, then t
SDECODE
(4 t
CLK
) is 1.96 µs. When SCLK is 16 MHz, one byte can be
transferred in 500 ns. This byte transfer time does not meet the t
SDECODE
specification; therefore, a delay must be
inserted so the end of the second byte arrives 1.46 µs later. If SCLK is 4 MHz, one byte is transferred in 2 µs.
Because this transfer time exceeds the t
SDECODE
specification, the processor can send subsequent bytes without
delay. In this later scenario, the serial port can be programmed to move from single-byte transfers per cycle to
multiple bytes.
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Product Folder Links: ADS131E04 ADS131E06 ADS131E08