Datasheet

f
SCLK
f (N )(N
DR BITS CHANNELS
) + 24
N =
DEVICES
DOUT
1
DAISY_IN
0
DOUT 0
CLKS
MSB
0
21 3 n n+1 n+2
LSB
0
n+3
Data From First Device (ADS131E04/6/8)
XX
MSB
1
LSB
1
MSB
1
LSB
1
Data From Second Device (ADS131E04/6/8)
ADS131E04
ADS131E06
ADS131E08
SBAS561A –JUNE 2012–REVISED APRIL 2013 www.ti.com
Note that from Figure 2, the SCLK rising edge shifts data out of the ADS131E0x on DOUT. The SCLK rising
edge is also used to latch data into the device DAISY_IN pin down the chain. This architecture allows for a faster
SCLK rate speed, but it also makes the interface sensitive to board-level signal delays. The more devices in the
chain, the more challenging it could become to adhere to setup and hold times. A star-pattern connection of
SCLK to all devices, minimizing length of DOUT, and other printed circuit board (PCB) layout techniques helps.
Placing delay circuits (such as buffers) between DOUT and DAISY_IN also helps mitigate this challenge. One
other option is to insert a D flip-flop between DOUT and DAISY_IN clocked on an inverted SCLK. Also note that
daisy-chain mode requires some software overhead to recombine data bits spread across byte boundaries.
Figure 38 shows a timing diagram for daisy-chain mode.
NOTE: n = (number of channels) × (resolution) + 24 bits. The number of channels is 4, 6, or 8. Resolution is 16-bit or 24-bit.
Figure 38. Daisy-Chain Timing
The maximum number of devices that can be daisy-chained depends on the data rate at which the device is
operated at. The maximum number of devices can be approximately calculated with Equation 7.
where:
N
BITS
= device resolution (depends on RDR[1:0] setting),
and N
CHANNELS
= number of channels in the device (4, 6, or 8). (7)
For example, when the ADS131E08 (eight-channel version) is operated at a 24-bit, 8-kSPS data rate with f
SCLK
=
10 MHz, up to six devices can be daisy-chained together.
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