Datasheet

START Opcode
START Pin
DIN
4/f
CLK
DRDY
or
t
DR
t
SETTLE
ADS131E04
ADS131E06
ADS131E08
SBAS561A –JUNE 2012–REVISED APRIL 2013 www.ti.com
START
The START pin must be set high (for a minimum of 2 t
CLK
s) or the START command sent to begin conversions.
When START is low, or if the START command has not been sent, the device does not issue a DRDY signal
(conversions are halted).
When using the START opcode to control conversion, hold the START pin low. In multiple device configurations
the START pin is used to synchronize devices (see the Multiple Device Configuration subsection of the SPI
Interface section for more details).
Settling Time
The settling time (t
SETTLE
) is the time it takes for the converter to output fully-settled data when the START signal
is pulled high. Once START is pulled high, DRDY is also pulled high. The next DRDY falling edge indicates that
data are ready. Figure 33 shows the timing diagram and Table 7 shows the settling time for different data rates.
The settling time depends on f
CLK
and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1
register). Table 5 shows the settling time as a function of t
CLK
. Note that when START is held high and there is a
step change in the input signal, it takes 3 t
DR
for the filter to settle to the new value. Settled data are available on
the fourth DRDY pulse.
Figure 33. Settling Time
Table 7. Settling Time for Different Data Rates
DR[2:0] SETTLING TIME UNIT
000 152 t
CLK
001 296 t
CLK
010 584 t
CLK
011 1160 t
CLK
100 2312 t
CLK
101 4616 t
CLK
110 9224 t
CLK
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