Datasheet

GPIO Pin
GPIO Data (Read)
GPIO Data (Write)
GPIO Control
DRDY
DOUT
SCLK
Bit 215 Bit 214 Bit 213
ADS131E04
ADS131E06
ADS131E08
www.ti.com SBAS561A –JUNE 2012–REVISED APRIL 2013
Figure 31 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an
ADS131E0x with a selected data rate that gives 16-bit resolution). DOUT is latched out at the SCLK rising edge;
DRDY is pulled high at the SCLK falling edge. Note that DRDY goes high on the first SCLK falling edge
regardless of whether data are being retrieved from the device or a command is being sent through the DIN pin.
For 24-bit resolution, the data starts from bit 215.
Figure 31. DRDY with Data Retrieval (CS = 0)
GPIO
The ADS131E0x have a total of four general-purpose digital I/O (GPIO) pins available in the normal mode of
operation. The digital I/O pins are individually configurable as either inputs or outputs through the GPIOC bits
register. The GPIOD bits in the GPIO register control the level of the pins. When reading the GPIOD bits, the
data returned are the logic level of the pins, whether they are programmed as inputs or outputs. When the GPIO
pin is configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an
output, a write to the GPIOD bit sets the output value.
If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on
or after a reset. Figure 32 shows the GPIO port structure. The pins should be shorted to DGND if not used.
Figure 32. GPIO Port Pin
Power-Down (PWDN)
When PWDN is pulled low, all on-chip circuitry is powered down. To exit power-down mode, take the PWDN pin
high. Upon exiting from power-down mode, the internal oscillator and the reference require time to wake up. It is
recommended that during power-down the external clock is shut down to save power.
Reset (RESET)
There are two methods to reset the ADS131E0x: pull the RESET pin low, or send the RESET opcode command.
When using the RESET pin, take it low to force a reset. Make sure to follow the minimum pulse width timing
specifications before taking the RESET pin back high. The RESET command takes effect on the eighth SCLK
falling edge of the opcode command. On reset it takes 18 t
CLK
cycles to complete initialization of the configuration
registers to the default states and start the conversion cycle. Note that an internal RESET is automatically issued
to the digital filter whenever the CONFIG1 register is set to a new value with a WREG command.
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Product Folder Links: ADS131E04 ADS131E06 ADS131E08