Datasheet

CS
SCLK
DRDY
DOUT STAT
24-Bit n-Bit n-Bit
CH1 CH2
DIN
n-Bit n-Bit n-Bit n-Bit n-Bit n-Bit
CH3 CH4 CH5 CH6 CH7 CH8
N SCLKS
ADS131E04
ADS131E06
ADS131E08
SBAS561A –JUNE 2012–REVISED APRIL 2013 www.ti.com
Data Output (DOUT)
The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS131E0x. Data
on DOUT are shifted out on the SCLK rising edge. DOUT goes to a high-impedance state when CS is high. In
read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line
also indicates when new data are available. This feature can be used to minimize the number of connections
between the device and system controller.
Figure 30 shows the ADS131E0x data output protocol.
NOTE: N SCLKs = (N bits)(N channels) + 24 bits. N-bit is dependent upon the DR[2:0] registry bit settings (N = 16 or 24).
Figure 30. ADS131E0x SPI Bus Data Output (Eight Channels)
Data Retrieval
Data retrieval can be accomplished in one of two methods. The read data continuous command (see the
RDATAC: Read Data Continuous section) can be used to set the device in a mode to read the data continuously
without sending opcodes. The read data command (see the RDATA: Read Data section) can be used to read
just one data output from the device (see the SPI Command Definitions section for more details). The conversion
data are read by shifting the data out on DOUT. The MSB of the data on DOUT is clocked out on the first SCLK
rising edge. DRDY returns to high on the first SCLK falling edge. DIN should remain low for the entire read
operation.
The number of bits in the data output depends on the number of channels and the number of bits per channel.
For the ADS131E0x with 32- and 64-kSPS data rates, the number of data outputs is [(24 status bits + 16 bits × 8
channels) = 152 bits]. The format of the 24 status bits is (1100 + FAULT_STATP + FAULT_STATN + GPIO[7:4]).
The data format for each channel data are twos complement and MSB first. When channels are powered down
using the user register setting, the corresponding channel output is set to '0'. However, the sequence of channel
outputs remains the same. The last four (ADS131E04) or two (ADS131E06) channel outputs shown in Figure 30
are '0's.
The ADS131E0x also provide a multiple readback feature. The data can be read out multiple times by simply
giving more SCLKs, in which case the MSB data byte repeats after reading the last byte. The DAISY_IN bit in
the CONFIG1 register must be set to '1' for multiple readbacks.
Data Ready (DRDY)
DRDY is an output. When it transitions low, new conversion data are ready. The CS signal has no effect on the
data ready signal. DRDY behavior is determined by whether the device is in RDATAC mode or the RDATA
command is being used to read data on demand. (See the RDATAC: Read Data Continuous and RDATA: Read
Data subsections of the SPI Command Definitions section for further details).
When reading data with the RDATA command, the read operation can overlap the next DRDY occurrence
without data corruption.
The START pin or the START command is used to place the device either in normal data capture mode or pulse
data capture mode.
26 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS131E04 ADS131E06 ADS131E08