Datasheet

MUX[2:0] = 101
TempP
MUX[2:0] = 100
MvddP
(1)
MUX[2:0] = 011
MUX[2:0] = 000
MUX[2:0] = 001
To PgaP
To PgaN
MUX[2:0] = 001
VINP
VINN
MUX[2:0] = 000
MvddN
(1)
TempN
MUX[2:0] = 100
MUX[2:0] = 101
Device
MUX
TestP
TestN
TESTP
INT_TEST
INT_TEST
TESTN
INT_TEST
INT_TEST
MUX[2:0] = 011
(VREFP + VREFN)
2
EMI
Filter
ADS131E04
ADS131E06
ADS131E08
www.ti.com SBAS561A –JUNE 2012–REVISED APRIL 2013
THEORY OF OPERATION
This section contains details of the ADS131E0x internal functional elements. The analog blocks are discussed
first, followed by the digital interface. Information on implementing power monitoring specific applications is
covered towards the end of this document.
Throughout this document, f
CLK
denotes the signal frequency at the CLK pin, t
CLK
denotes the signal period at the
CLK pin, f
DR
denotes the output data rate, t
DR
denotes the output data time period, and f
MOD
denotes the
frequency at which the modulator samples the input.
EMI FILTER
An RC filter at the input acts as an EMI filter on all channels. The –3-dB filter bandwidth is approximately
3 MHz.
INPUT MULTIPLEXER
The ADS131E0x input multiplexers are very flexible and provide many configurable signal switching options.
Figure 17 shows a diagram of the multiplexer on a single channel of the device. VINP and VINN are separate for
each of the eight blocks. This flexibility allows for significant device and sub-system diagnostics, calibration, and
configuration. Switch settings for each channel are selected by writing the appropriate values to the CHnSET
register (see the CHnSET Register in the Register Map section for details.)
(1) MVDD monitor voltage supply depends on channel number; see the Supply Measurements (MVDDP, MVDDN) section.
Figure 17. Input Multiplexer Block for One Channel
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Product Folder Links: ADS131E04 ADS131E06 ADS131E08