Datasheet

MUX[2:0] = 101
TempP
MUX[2:0] = 100
MVDDP
MUX[2:0] = 011
From LOFFP
MAIN
(1)
MUX[2:0] = 110
MUX[2:0] = 001
To PGAP
To PGAN
MUX[2:0] = 001
MUX[2:0] = 111
VINP
VINN
MAIN
(1)
AND SRB1
From LoffN
(AVDD+AVSS)
2
MVDDN
TempN
Device
MUX
INT_TEST
(VREFP + VREFN)
2
TESTP
INT_TEST
TESTM
SRB2 BIAS_IN
To Next Channels
CHxSET[3] = 1
SRB1
To Next Channels
MAIN
(1)
AND SRB1
MUX[2:0] = 010 AND
BIAS_MEAS
MUX[2:0] = 010
AND
BIAS_MEAS
BIASREF_INT=1
BIASREF_INT=0
MUX[2:0] = 100
MUX[2:0] = 011
MUX[2:0] = 101
BIASREF
ADS1299
SBAS499A –JULY 2012–REVISED AUGUST 2012 www.ti.com
THEORY OF OPERATION
This section contains details of the ADS1299 internal functional elements. The analog blocks are discussed first,
followed by the digital interface. Blocks implementing EEG-specific functions are covered at the end of this
document.
Throughout this document, f
CLK
denotes the CLK pin signal frequency, t
CLK
denotes the CLK pin signal period,
f
DR
denotes the output data rate, t
DR
denotes the output data time period, and f
MOD
denotes the frequency at
which the modulator samples the input.
INPUT MULTIPLEXER
The ADS1299 input multiplexers are very flexible and provide many configurable signal-switching options.
Figure 19 shows the multiplexer on a single channel of the device. Note that the device has eight such blocks,
one for each channel. SRB1, SRB2, and BIASIN are common to all eight blocks. VINP and VINN are separate
for each of the eight blocks. This flexibility allows for significant device and sub-system diagnostics, calibration,
and configuration. Switch setting selections for each channel are made by writing the appropriate values to the
CHnSET[3:0] register (see the CHnSET: Individual Channel Settings section for details) by writing the
BIAS_MEAS bit in the CONFIG3 register and the SRB1 bit in the MISC1 register (see the CONFIG3:
Configuration Register 3 subsection of the Register Map section for details). Refer to the Input Multiplexer
subsection of the EEG-Specifc Functions section for further information regarding the EEG-specific features of
the multiplexer.
(1) MAIN is equal to either MUX[2:0] = 000, MUX[2:0] = 110, or MUX[2:0] = 111.
Figure 19. Input Multiplexer Block for One Channel
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