User's Guide SLAU443 – May 2012 EEG Front-End Performance Demonstration Kit This user's guide describes the characteristics, operation, and use of the ADS1299EEG-FE. This EVM is an evaluation module for the ADS1299, an eight-channel, 24-bit, low-power; integrated analog front-end (AFE) designed for electroencephalography (EEG) applications. The ADS1299ECG-FE is intended for prototyping and evaluation. This user's guide includes a complete circuit description, schematic diagram, and bill of materials.
www.ti.com 8 9 7.2 Lead-Off Detection ............................................................................................... 7.3 External Calibration/Test Signals ............................................................................... Test Options on the EVM ................................................................................................. 8.1 On Chip (ADS1299) Input Short ................................................................................ 8.
www.ti.com 36 Dedicated Reference and Bias Electrode .............................................................................. 33 37 Programmable reference and bias electrode .......................................................................... 34 38 Settings for Normal Electrode............................................................................................ 35 39 Configuring BIASREF and Bias Drive Buffer .........................................................................
ADS1299EEG-FE Overview www.ti.com 1 ADS1299EEG-FE Overview 1.1 Important Disclaimer Information CAUTION Notice: The ADS1299EEG-FE is intended for feasibility and evaluation testing only in laboratory and development environments. This product is not for diagnostic use. The ADS1299EEG-FE is to be used only under these conditions: • The ADS1299EEG-FE is intended only for electrical evaluation of the features of the ADS1299 device in a laboratory, simulation, or development environment.
Overview www.ti.com 2 Overview 2.1 Introduction The ADS1299EEG-FE is intended for evaluating the ADS1299 low-power, low noise 24-bit, simultaneously sampling, eight-channel front-end for EEG applications. The digital SPI™ control interface is provided by the MMB0 Modular EVM motherboard (Rev. D or higher) that connects to the ADS1299EEG FE evaluation board (Rev A).
Overview www.ti.com Figure 1. ADS1299EEG-FE Kit The complete kit includes the following items: • ADS1299EEG FE printed circuit board (PCB), Rev A • MMB0 (Modular EVM motherboard, Rev D or higher) • Universal ac to dc wall adapter, 120V to 240V ac to +6V dc 2.5 Factory Default Jumper Settings Table 1. Factory Default Jumper Settings Jumper Name Settings 6 Comment JP1 Not Installed Used for programmable bias drive.
Software Installation www.ti.com Table 1. Factory Default Jumper Settings (continued) Jumper Name Settings JP25 Comment 1-2/ 3-4/5-6 – BIAS_ELEC connected to all INPs – BIAS_ELEC connected to all INMs – BIAS_ELEC shorted to REF_ELEC which connects to SRB1 J6 5-6/ 7-8/ 9-10/ … 32-34 / 35-36 3 Software Installation 3.
Software Installation www.ti.com Figure 3. Initialization of ADS1299EEG-FE You must accept the license agreement (shown in Figure 4) before you can proceed with the installation. Figure 4.
Software Installation www.ti.com Figure 5. Installation Process Figure 6.
Software Installation www.ti.com Figure 7. Completion of ADS1299 Software Installation 3.3 Install the ADS1299 EVM Hardware Drivers Apply power to the MMB0 using the supplied wall mount power supply and connect the MMB0 to your PC via any available USB port. There are two USB drivers which will be installed. Follow the steps shown in the figures below to install the USB drivers. Figure 8.
Software Installation www.ti.com Figure 9. New Hardware Wizard Screen 3 Click Next and allow the wizard to find and install the driver. Figure 10.
Software Installation 3.3.1 www.ti.com Initial Launch of the ADS1299EEG FE Software Launch ADS1299EEG FE software from the program menu. The software will load and begin downloading firmware to the processor on data capture card (MMB0). Once the firmware is loaded and running, it will cause the USB to re-enumerate. Figure 11. Second 'New Hardware" Wizard Click Next Figure 12.
ADS1299EEG-FE Daughter Card Hardware Introduction www.ti.com By this time the ADS1299EEG FE software will have prompted the user an with error message. Click ‘OK’. It may be necessary to close the program, power cycle the ADS1299EEG FE and restart the program. This process may need to be done again should you plug the ADS1299ECG FE into a different USB port on your computer.
ADS1299EEG-FE Daughter Card Hardware Introduction www.ti.com Figure 13. ADS1299 EEG-FE Front End Block Diagram The ADS1299EEG-FE board is a four-layer circuit board. The board layout is provided in Section 9; the schematics are appended to this document. The following sections explain some of the hardware settings possible with the EVM for evaluating the ADS1299 under various test conditions. 4.1 Power Supply The EEG front-end EVM mounts on the MMB0 EVM with connectors J2, J3 and J4.
ADS1299EEG-FE Daughter Card Hardware Introduction www.ti.com Table 2. Power Supply Test Points Test Point Voltage TP7 +5.0V TP9 +1.8V TP10 +3.3V TP5 +5.0V TP13 +2.5V TP6 –2.5V TP8 GND The front-end board must be properly configured in order to achieve the various power-supply schemes. The default power-supply setting for the ADS1299EEG-FE is a unipolar analog supply of 5V and DVDD of either +3V or +1.8V.
ADS1299EEG-FE Daughter Card Hardware Introduction www.ti.com A 2.048MHz oscillator available for +3V and +1.8V DVDD is the FXO-HC735-2.048MHz and SiT8002AC34-18E-2.048, respectively. The EVM is shipped with the external oscillator enabled. 4.3 Reference The ADS1299 has an on-chip internal reference circuit that provides reference voltages to the device. Alternatively, the internal reference can be powered down and VREFP can be applied externally.
www.ti.com 4.6 ADS1299EEG-FE Daughter Card Hardware Introduction Analog Inputs The ADS1299EEG-FE is designed so that it can be used as a eight channel data acquisition board. Arbitrary input signals can be fed to the ADS1299 by feeding the signal directly at connector J6. Figure 14 shows the input configurations that are available in the EVM. Figure 14. Input Configurations Supported by the EEG-FE a) Differential Inputs b) Single ended inputs 4.6.1 Differential Inputs To 1. 2. 3.
Using the Software: ADS1299 Control Registers and GUI www.ti.com Apart from providing the option to feed inputs directly at the jumper (for general purpose data acquisition), the ADS1299 EVM provides multiple configurations specific to the EEG application. These configurations are explained in detail in Section 7. 5 Using the Software: ADS1299 Control Registers and GUI Before starting to use the EVM software, there is one important feature that users should be aware of.
Using the Software: ADS1299 Control Registers and GUI www.ti.com • • 5.
Using the Software: ADS1299 Control Registers and GUI www.ti.com Figure 17. Input Multiplexer for a Single Channel (MAIN = [000 or 110 or 111]) Figure 18.
Using the Software: ADS1299 Control Registers and GUI www.ti.com Figure 19. Register Bit for SRB1 Routing 5.3.1 Internal Test Signals Input Configuration Register 2 controls the signal amplitude and frequency of an internally-generated square wave test signals. The primary purpose of this test signal is to verify the functionality of the front-end MUX, the PGA, and the ADC. The test signals may be viewed on the Analysis→Scope tab, as Figure 20 shows.
Using the Software: ADS1299 Control Registers and GUI www.ti.com Figure 21. Simplified Diode Arrangement The output voltage corresponding to a given temperature can be read selecting the Temperature Sensor option on the Channel Control Registers GUI (see Figure 17) and verified using the Analysis→Scope tab as shown in Figure 22. The number 0.146V (on the y-axis) can be calculated as a temperature using Equation 1: Temperature = (0.146 – 0.145300) / 0.00049 + 25 = 26.
Using the Software: ADS1299 Control Registers and GUI www.ti.com 5.3.3 Normal Electrode Input The Normal electrode input on the MUX routes the inputs (VINP and VINN) differentially to the internal PGA, as Figure 17 illustrates. An exception is if the SRB1 bit is set high. If channel is in Normal electrode mode and SRB1 bit is set high the signal on SRB1 pin is routed to negative inputs of all channels instead of VINN inputs. 5.3.
Using the Software: ADS1299 Control Registers and GUI 5.5.1 www.ti.com Lead-Off Sense (LOFF_SENSP and LOFF_SENSN) Registers These registers enable lead-off detection for both the positive and negative channels. Figure 24 describes the 4-bit DAC settings to configure the lead-off threshold. Note that the LOFF_FLIPx bits change the direction of the lead-off current if this option is selected. Figure 24 illustrates the connections from the positive and negative inputs to the lead-off comparators.
Using the Software: ADS1299 Control Registers and GUI www.ti.com 5.5.2 Lead-Off Status Registers (LOFF_STATP and LOFF STATN) These registers store the output of the lead-off comparator that corresponds with each input. When a lead is disconnected, the corresponding register bit activates low. The GUI for this feature is enabled by clicking in the upper right-hand corner of the EVM software on the Show/Poll Lead-Off Status button.
Using the Software: ADS1299 Control Registers and GUI www.ti.com Figure 27. BIAS_SENSP and BIAS_SENSN GUI Panel 5.6 Register Map The Register Map→ Device Registers tab is a helpful debug feature that allows the user to view the state of all the internal registers. This tab is illustrated in Figure 28. Figure 28.
ADS1299EEG-FE Analysis Tools www.ti.com 6 ADS1299EEG-FE Analysis Tools Under the Analysis tab in the ADS1299EEG-FE GUI software, there are four different analysis tools shown that enable a detailed examination of the signals selected by the front-end MUX: • Scope • Analysis • Histogram • FFT These tools are detailed in the following subsections. 6.1 6.1.
ADS1299EEG-FE Analysis Tools www.ti.com Figure 30. Zoom Option on the Waveform Examination Tool 6.2 Histogram Tool The Histogram tool is located under the Analysis→Histogram tab. 6.2.1 Using the Analysis→Histogram Tool The Analysis→Histogram tool is used primarily to view the bin separation of the different amplitudes of the EEG waveform harmonics. Figure 31 illustrates the histogram output for input short on all channels.
ADS1299EEG-FE Analysis Tools www.ti.com Figure 31. Histogram Bins for Input Short Noise 6.3 FFT Tool The FFT tool is located under the Analysis→FFT tab. 6.3.1 Using the Analysis→FFT Tool The Analysis→FFT tool allows the user to examine the channel-specific spectrum as well as typical figures of merit such as SNR, THD, ENOB, and CMRR. Each feature is numbered below and described in detail in the following subsections. Figure 32 illustrates an Analysis→FFT plot for input short configuration.
ADS1299EEG-FE Analysis Tools www.ti.com Figure 32.
ADS1299EEG-FE Analysis Tools www.ti.com Figure 33. Analysis : FFT : AC Analysis Parameters : Windowing Options FFT Analysis: 3 Pressing the FFT Analysis button pulls up the window shown in Figure 34. This window can be useful because the different tabulated figures of merit can show more detailed information about the channel-tochannel noise. Figure 34.
EEG Specific Features www.ti.com Figure 35. Changing the User-Defined Dynamic Range for Channel 1 Input Amplitude: 5 This field is a user input that is important for accurately calculating the CMRR of each channel. 7 EEG Specific Features This section describes some of the EEG specific features supported by the EVM, including the reference/patient bias signals, lead off detection and calibration. 7.
EEG Specific Features www.ti.com Figure 36. Dedicated Reference and Bias Electrode Reference : The reference electrode (REF_ELEC) input is used to drive the negative inputs of the channel through SRB1 pin on ADS1299 device. The reference electrode is connected to the negative inputs of all the channels. This leads to increased leakage current on the reference electrode since current of all the channels gets added. The EVM provides an option to buffer the reference electrode to reduce the leakage.
EEG Specific Features 7.1.2 www.ti.com Programmable Reference and Bias Electrodes The multiplexer in ADS1299 allows any electrode to be chosen as the bias electrode or reference electrode. This is illustrated in Figure 37. Figure 37. Programmable reference and bias electrode The reference electrode selection is done using SRB2 pin. The SRB2 bit in CHxSET register is set high for the electrode chosen as reference.
EEG Specific Features www.ti.com The reference voltage for the on-chip right leg drive can be driven externally. The on-chip voltage is set to mid-supply. If the application requires the common mode to be set to any other voltage, this configuration can be accomplished by setting the appropriate bit in the Configuration 3 Register. The external BIASREF voltage is set by resistor R1 and adjustable resistor R2. The following procedure needs to be applied to activate the Bias drive circuitry: Step 1.
EEG Specific Features www.ti.com Figure 40. Setting up the Bias Drive Loop Once these steps are completed, measure and verify that the voltage on either side of R8 is close to midsupply. This measurement confirms whether the Bias drive loop is functional. Apart from the BIAS_DRV signal, the ADS1299EEG-FE also offers an option to drive the cable shield. The EEG cable shield signal can be connected to BIAS_SHD. The jumper (1-2) on JP17 must be shorted to enable the shield drive.
EEG Specific Features www.ti.com Figure 41. Setting the LOFF Register Bits Step 3. Turn on the lead-off comparator by setting the bit in the Configuration 4 Register in the Global Registers control tab, as Figure 42 shows. Figure 42. Configuring the Lead Off Comparator Step 4. The software has an option where the LOFF_STATP and LOFF_STATM Registers are continuously polled (set the Read Status Registers switch as shown in shown in Figure 43).
EEG Specific Features 7.2.2 www.ti.com AC Lead-Off Detection AC lead off detection can be used in three ways 1. To measure electrode impedance with inband excitation for one time use at electrode placement. 2. To simultaneously measure electrode impedance with EEG, by using out of band excitation. 3. To detect if a lead is off for an AC coupled input. These options are explained below. In band Electrode impedance measurement ADS1299 provides two frequency options (7.8Hz and 31.
EEG Specific Features www.ti.com Figure 45. FFT Analysis for Impedance Measurement at 31.25Hz Out of band Lead off detection ADS1299 also provides option to do electrode impedance measurement at frequencies outside the EEG bandwidth of interest. The frequency for this AC current source is set at fDR/4. For example to do an AC lead-off detection at 1 kHz the data rate for the device must be set at 4Ksps. These measurements can be done concurrently with the EEG measurement.
EEG Specific Features www.ti.com Figure 46. Scope Tab for Impedance Measurement at fDR/4 (DR = 4ksps) 7.3 External Calibration/Test Signals ADS1299 generates a square wave test signal that can be used to check the functionality of the signal chain (Refer to the datasheet for details). It also gives the user an option to provide external test signals for calibration. For evaluation purposes with the EVM, the test signals can be provided directly to the jumpers of the corresponding signals.
EEG Specific Features www.ti.com Figure 47. Multiplexer Setting for Calibration with Electrode Disconnected 7.3.2 Channel Inputs Connected It may sometimes be required to provide a calibration or test signal to ADS1299 device with the positive input connected to the pin or electrode. This can be accomplished by connecting the positive test signal to SRB2 pin and the negative test signal to SRB1 pin.
EEG Specific Features www.ti.com Figure 48. Multiplexer Setting with Positive Electrode Connected to Test Signal If it is desired to have both the input pins connected during calibration or test, the following connections must be made. The positive test signal must be tied to SRB2 pin and the negative test signal must tie to BIASIN pin. The channel multiplexer must be set for 111 and the SRB2 switch must be closed. This multiplexer setting is illustrated in Figure 49. Figure 49.
Test Options on the EVM www.ti.com 8 Test Options on the EVM 8.1 On Chip (ADS1299) Input Short The channel input can be shorted internally by setting the input multiplexer of the individual channel to 001. The global registers must be set as shown in Figure 51. The channel control registers must be set as shown in Figure 50. This test gives the noise in the channel. It also gives the offset in the channel. The result can be seen in the analysis tab.
Test Options on the EVM www.ti.com Figure 52. Scope Tab for Input Short Test 8.2 External Input Short with 5K Resistor There is an option on board to tie the positive and negative input of the channel to a common voltage (VCM) on BIAS_ELEC through 5K resistors. The following jumper settings are needed for this test. On JP6 short pin 1 and pin 2. On JP25 short (1-2) and (2-3). The connecter J6 must have jumpers across from left to right to connect the inputs to the ADS1299 channels.
Test Options on the EVM www.ti.com Figure 53. Global Register Settings for External Input Short Test Figure 54.
Test Options on the EVM 8.3 www.ti.com Noise with Common Reference on Negative Inputs There is an option in ADS1299 to connect all the channels negative inputs to a common reference. This can be accomplished by giving a signal on SRB1 pin and setting the bit SRB1 bit in MISC1 register. There is an option on board to test out the channel noise performance with this setting. On JP81 a jumper on (34) and (5-6) is needed. On JP8 a jumper (1-2) is required.
Test Options on the EVM www.ti.com Figure 56.
Test Options on the EVM 8.4 www.ti.com Noise with Buffered Common Reference Input Connecting all the negative inputs to one reference electrode can lead to excessive leakage current on the electrode. The typical leakage current on ADS1299 channel is 200pA. So for a 16 channel system total leakage may be as large as 3.2nA. This number will become progressively worse as channel count is increased.
Test Options on the EVM www.ti.com 8.5 Internally Generated Test Signal and Other Multiplexer Inputs ADS1299 internally generates a test signal that can be used for signal integrity check. Also the multiplexer provides options to measure supply voltage, temperature, etc. Details of these inputs can be found in Section 5.3. 8.6 Arbitrary Input Signal Any input signal can be fed to the device on connector J6 as described in Section 4.6.
Bill of Materials, Layouts and Schematics 9 www.ti.com Bill of Materials, Layouts and Schematics This section contains the complete bill of materials, printed circuit board (PCB) layouts, and schematic diagrams for the ADS1299EEG-FE. NOTE: Board layouts are not to scale. These are intended to show how the board is laid out; do not use for manufacturing ADS1299EEG-FE PCBs. 9.1 ADS1299EEG-FE Front-End Board Schematics Figure 59 through Figure 63 shown the schematic diagrams of the ADS1299EEG-FE.
Bill of Materials, Layouts and Schematics www.ti.com R80 4.99K AIN8N C80 4.7nF AGND C81 4.7nF 4.99K AIN8P R81 R82 4.99K AIN7N C82 4.7nF AGND C83 4.7nF 4.99K AIN7P R83 R84 4.99K AIN6N C84 4.7nF AGND C85 4.7nF 4.99K AIN6P R85 R86 R12 4.99K J6 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 AIN1 5 4 3 2 1 AGND 4.99K BIAS_SHD 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 AIN5N C86 4.7nF AGND C87 4.7nF 4.99K AIN5P R87 R88 4.99K AIN4N C88 4.7nF AGND C89 4.7nF 4.
Bill of Materials, Layouts and Schematics www.ti.com C48 5 3 1uF 10uF 1uF IN OUT 1 AGND VCC_-5v 3.3uH C49 C50 1uF 10uF C51 10uF AGND TPS60403 AGND 4 AGND C47 L2 GND 10uF C46 CFLY- 2 3.3uH CFLY+ L1 C45 TP4 U6 VCC_5v AGND TP5 +5.0V JP2 AVDD C57 0.1uF TP13 U9 1 IN OUT L5 5 C58 1uF 3 EN C59 C60 2.2uF 10uF +2.5V 3.3uH 10uF R56 AGND NI 2 AGND C61 GND NR/FB AGND AGND 4 C62 TPS73225 R57 1uF NI AGND AGND TP6 U8 VCC_-5v 2 IN OUT L4 5 C63 2.
Bill of Materials, Layouts and Schematics www.ti.com R50 NI C40 NI AVDD 7 C41 NI 3 C34 4 NI VIN 7 R49 NI OUT R47 6 C35 TEMP GND 3 6 R51 JP3 NI NI VREFP NI R48 NI NI NI TRIM U5 4 2 N/C 2 N/C 1 AVDD N/C 8 8 AGND U3 NI C38 NI 5 C43 C39 NI C42 NI AVSS AGND NI AVSS AVSS Figure 62.
Bill of Materials, Layouts and Schematics www.ti.com Figure 64. ADS1299EEG-FE Top Assembly Figure 65.
Bill of Materials, Layouts and Schematics www.ti.com Figure 66. ADS1299EEG-FE Internal Layer (1) Figure 67.
Bill of Materials, Layouts and Schematics www.ti.com Figure 68. ADS1299EEG-FE Bottom Layer Figure 69.
Bill of Materials, Layouts and Schematics www.ti.com 9.3 Bill of Materials Table 10 lists the bill of materials for the ADS1299ECG-FE. Table 10.
Bill of Materials, Layouts and Schematics www.ti.com Table 10. Bill of Materials (continued) Qty Ref Des Description MFR Part Number 5 TP1, TP2, TP8, TP11, TP12 TEST POINT PC MINI .040"D BLACK Keystone 5001 8 TP3, TP4, TP5, TP6, TP7, TP9, TP10, TP13 TEST POINT PC MINI .040"D RED Keystone 5000 1 U1 ADS1299, Low-Noise, 8-Channel, 24-bit analog Front-End for Biopotential Measurements TI ADS1299CPAG 0 U2 Not Installed 0 U3, U5 Not Installed 2 U4, U11 IC OP AMP GP 5.
Bill of Materials, Layouts and Schematics www.ti.com 9.4 ADS1299EEG-FE Power-Supply Recommendations Figure 70 shows a +6V power-supply cable (not provided in the EVM kit) connected to a battery pack with four 1.5V batteries connected in series. Connecting to a wall-powered source (provided in the EVM kit) makes the ADS1299EEG-FE more susceptible to 50Hz/60Hz noise pickup; therefore, for best performance, it is recommended to power the ADS1299EEG-FE with a battery source.
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods.
FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
【Important Notice for Users of this Product in Japan】 】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.
EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use.
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods.
FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
【Important Notice for Users of this Product in Japan】 】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.
EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.