Datasheet

ADS1294, ADS1294R
ADS1296, ADS1296R
ADS1298, ADS1298R
SBAS459I –JANUARY 2010–REVISED JANUARY 2012 www.ti.com
CONFIG1: Configuration Register 1
Address = 01h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
HR DAISY_EN CLK_EN 0 0 DR2 DR1 DR0
Bit 7 HR: High-Resolution/Low-Power mode
This bit determines whether the device runs in Low-Power or High-Resolution mode.
0 = Low-Power mode (default)
1 = High-Resolution mode
Bit 6 DAISY_EN: Daisy-chain/multiple readback mode
This bit determines which mode is enabled.
0 = Daisy-chain mode (default)
1 = Multiple readback mode
Bit 5 CLK_EN: CLK connection
(1)
This bit determines if the internal oscillator signal is connected to the CLK pin when the CLKSEL pin = 1.
0 = Oscillator clock output disabled (default)
1 = Oscillator clock output enabled
Bits[4:3] Must always be set to '0'
Bits[2:0] DR[2:0]: Output data rate
For High-Resolution mode, f
MOD
= f
CLK
/4. For low power mode, f
MOD
= f
CLK
/8.
These bits determine the output data rate of the device.
(1) Additional power is consumed when driving external devices.
BIT DATA RATE HIGH-RESOLUTION MODE
(1)
LOW-POWER MODE
(2)
000 f
MOD
/16 32kSPS 16kSPS
001 f
MOD
/32 16kSPS 8kSPS
010 f
MOD
/64 8kSPS 4kSPS
011 f
MOD
/128 4kSPS 2kSPS
100 f
MOD
/256 2kSPS 1kSPS
101 f
MOD
/512 1kSPS 500SPS
110 (default) f
MOD
/1024 500SPS 250SPS
111 Do not use n/a n/a
(1) Additional power is consumed when driving external devices.
(2) f
CLK
= 2.048MHz.
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Product Folder Link(s): ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R