Datasheet

f
SCLK
f (N )(N
DR BITS CHANNELS
)+24
N =
DEVICES
ADS1294, ADS1294R
ADS1296, ADS1296R
ADS1298, ADS1298R
www.ti.com SBAS459I –JANUARY 2010–REVISED JANUARY 2012
In a case where all devices in the chain operate in the same register setting, DIN can be shared as well and
thereby reduce the SPI communication signals to four, regardless of the number of devices. However, because
the individual devices cannot be programmed, the RLD driver cannot be shared among the multiple devices.
Furthermore, an external clock must be used.
Note that from Figure 2, the SCLK rising edge shifts data out of the ADS129x on DOUT. The SCLK rising edge is
also used to latch data into the device DAISY_IN pin down the chain. This architecture allows for a faster SCLK
rate speed, but it also makes the interface sensitive to board level signal delays. The more devices in the chain,
the more challenging it could become to adhere to setup and hold times. A star pattern connection of SCLK to all
devices, minimizing length of DOUT, and other PCB layout techniques help. Placing delay circuits such as
buffers between DOUT and DAISY_IN are ways to mitigate this challenge. One other option is to insert a D
flip-flop between DOUT and DAISY_IN clocked on an inverted SCLK. Note also that daisy-chain mode requires
some software overhead to recombine data bits spread across byte boundaries.
The maximum number of devices that can be daisy-chained depends on the data rate at which the device is
being operated. The maximum number of devices can be estimated with Equation 7.
where:
N
BITS
= device resolution (depends on data rate), and
N
CHANNELS
= number of channels in the device (4, 6, or 8). (7)
For example, when the ADS1298 (eight-channel, 24-bit version) is operated at a 2kSPS data rate with a 4MHz
f
SCLK
, 10 devices can be daisy-chained.
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Product Folder Link(s): ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R