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ADS1298ECG-FE/ADS1198ECG-FE Hardware Details

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5.1 Jumper Description

Table 5 shows the jumpers on the ADS1298ECG-FE and options available for each jumper.

Table 5. ADS1x98ECG-FE Default Jumper/Switch Configuration

Jumper Function Settings

JP1 Installed RLD feedback

1-2: AVDD selected for bipolar supply operation (AVDD = +2.5V)

JP2 AVDD supply source

2-3: AVDD selected for single supply operation (AVDD = +3.0V)

External Reference Connection Open: External reference not connected

JP3

(Header Not Installed)

(1)

Installed: External reference connected

Connect EVM +5V rail to Open: EVM +5V must be supplied externally

JP4

J4(power header) Installed: EVM +5V supplied from J4 (power header)

Open: PWDN pin controlled from J5 header (pulled up to DVDD)

JP5 PWDN source

Installed: Device is powered down (PWDN pin = AGND)

1-2: DC-coupled input signals (Pins 1-2 shorted on PCB)

JP6 to Input signal DC/AC couples

2-3: AC-coupled input signals (Requires installation of header and cutting PCB

JP114 (Header Not Installed)

short of pin 1-2)

1-2: ECG shield is grounded (AGND)

JP15 ECG shield drive connected 2-3: ECG shield is connected to buffer (required U2 installation, otherwise shield

connection is open)

Open: WCT NOT connected to JP26-30 and JP33

Wilson Central Terminal (WCT)

JP16 Installed: WCT connected to JP26-30 and JP33 for connection to CH1 and CH4-8

connection

IN-

ECG shield drive buffer 1-2: ECG shield drive connected to RLDOUT

JP17

input(Header Not Installed)

(2)

2-3: ECG shield drive connected to RLDINV

1-2: CLK connected to DSP (J3.17)

JP18 CLK connection

2-3: CLK connected to OSC1

1-2: OSC1 enabled

JP19 OSC1 Enable

2-3: OSC1 disabled

1-2: AVSS selected for single supply operation (AVSS = 0V (AGND))

JP20 AVSS supply source

2-3: AVSS selected for bipolar supply operation (AVSS = -2.5V)

1-2: CS connected to DSP via J3.1

JP21 CS source

2-3: CS connected to DSP via J3.7

1-2: START comes from J3.1

JP22 START source

2-3: START comes from J3.14

1-2: External Master Clock

JP23 CLKSEL source

2-3: Internal Master Clock (CLKSEL controlled by J3.2 (pulled up to DVDD))

1-2: DVDD supply = 1.8V

JP24 DVDD Supply Select

2-3: DVDD supply = 3.3V

External Reference Selection 1-2: Select U4 as reference source

JP25

(Header Not Installed)

(3)

2-3: Selected U3 as reference source