Datasheet
ADS1293
www.ti.com
SNAS602B –FEBRUARY 2013–REVISED MARCH 2013
TIMING DIAGRAMS
Unless otherwise noted, all limits specified at T
A
= 25°C, +2.7V ≤ VDD ≤ +5.5V, +1.65 ≤ VDDIO ≤ MIN(+3.6V,
VDD), VREF = +2.4V, f
OSC
= 409.6kHz and a 10pF capacitive load in parallel with a 10kΩ load on SDO.
Figure 1. Write Timing Diagram
PARAMETER CONDITIONS MIN TYP MAX UNIT
F
SCLK
Serial Clock Frequency 20 MHz
t
PH
SCLK Pulse Width - High F
SCLK
= 20MHz 0.4/F
SCLK
s
t
PL
SCLK Pulse Width - Low F
SCLK
= 20MHz 0.4/F
SCLK
s
t
SU
SDI Setup Time 5 ns
t
H
SDI Hold Time 5 ns
Figure 2. Read Timing Diagram
PARAMETER CONDITIONS MIN TYP MAX UNIT
t
ODZ
SDO Driven-to-Tristate Time Measured at 10% / 90% point 15 ns
t
OZD
SDO Tristate-to-Driven Time Measured at 10% / 90% point 15 ns
t
OD
SDO Output Delay Time 10 ns
t
CSS
CSB Setup Time 5 ns
t
CSH
CSB Hold Time 5 ns
t
IAG
Inter-Access Gap 10 ns
t
DRDYB
Data Ready Bar at every 1/ODR second, see 4/f
OSC
s
Figure 25
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