Datasheet

ADS1293
SNAS602B –FEBRUARY 2013–REVISED MARCH 2013 www.ti.com
ELECTRICAL CHARACTERISTICS
(1)
(continued)
Unless otherwise noted, all limits are specified at T
A
= +25°C, +2.7V ≤ VDD ≤ +5.5V, +1.65V ≤ VDDIO ≤ MIN(+3.6V, VDD),
VREF = +2.4V, f
OSC
= 409.6kHz, 1µF low ESR capacitor between CVREF and GND, 0.1µF capacitor between RLDREF and
GND. Boldface limits apply for T
MIN
≤ T
A
≤ T
MAX
.
PARAMETER TEST CONDITIONS MIN
(2)
TYP
(3)
MAX
(2)
UNIT
ANALOG PACE CHANNEL
Gain 3.5 V/V
BW -3dB Bandwidth 50 kHz
Output Reference RLDREF V
V
OS
Input-Referred Offset Voltage ±1.3 mV
2.7V ≤ VDD < 3.3V –330 330 mV
DIVR Differential Input Voltage Range
3.3V ≤ VDD –400 400 mV
Common-Mode Voltage Range for full
CMVR 0.95 VDD – 1.1 V
DIVR
CMRR Common-Mode Rejection Ratio 0.5V ≤ VCM ≤ VDD-1.5V 85 dB
PSRR Power Supply Rejection Ratio 3V ≤ VDD ≤ 5V, VCM=RLDREF 80 dB
SR Slew Rate 35 mV/µs
Overload Recovery 100 µs
V
e
-APACE Input-Referred Noise for Analog Pace VCM = RLDREF, 0.1kHz - 20kHz 105 µV
PP
IVDD Current Consumption 29 µA
CLOCK
f
OSC
Internal Clock Frequency f
CRYSTAL
= 4.096MHz 409.6 kHz
Internal Clock Duty Cycle 50%
TSTART Internal Clock Start up Time f
CRYSTAL
= 4.096MHz 15 ms
IVDD Internal Clock Power Consumption 83 µA
f
EXT
External Clock Frequency
(5)
370 409.6 450 kHz
External Clock Duty Cycle
(5)
40% 50% 60%
DIGITAL INPUT/OUTPUT CHARACTERISTICS
0.8 ×
V
IH
Logical “1” Input Voltage V
VDDIO
0.2 ×
V
IL
Logical “0” Input Voltage V
VDDIO
VDDIO –
I
SOURCE
= 400 µA, Digital output high drive mode
0.075
V
OH
Logical “1” Output Voltage V
VDDIO –
I
SOURCE
= 400 µA, Digital output low drive mode
0.15
I
SINK
= 400 µA Digital output high drive mode VSSIO + V
0.075
V
OL
Logical “0” Output Voltage
I
SINK
= 400 µA Digital output low drive mode VSSIO + V
0.15
SYNCB and RESETB pins, with 1 MΩ internal pull- ±1 µA
up resistor
I
IOHL
Digital IO Leakage Current
Other digital I/O pins ±500 nA
(5) Specified by design; not production tested.
8 Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ADS1293