Datasheet

ADS1293
SNAS602B –FEBRUARY 2013–REVISED MARCH 2013 www.ti.com
Table 56. CH_CNFG: Configure Channel for Loop Read Back Mode
Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x2F E3_EN E2_EN E1_EN P3_EN P2_EN P1_EN STS_EN
[7] RESERVED —
[6] E3_EN Enable DATA_CH3_ECG read back
0: Disable data read back for this channel (default)
1: Enable data read back for this channel
[5] E2_EN Enable DATA_CH2_ECG read back
0: Disable data read back for this channel (default)
1: Enable data read back for this channel
[4 ] E1_EN Enable DATA_CH1_ECG read back
0: Disable data read back for this channel (default)
1: Enable data read back for this channel
[3] P3_EN Enable DATA_CH3_PACE read back
0: Disable data read back for this channel (default)
1: Enable data read back for this channel
[2] P2_EN Enable DATA_CH2_PACE read back
0: Disable data read back for this channel (default)
1: Enable data read back for this channel
[1] P1_EN Enable DATA_CH1_PACE read back
0: Disable data read back for this channel (default)
1: Enable data read back for this channel
[0] STS_EN Enable DATA_STATUS read back
0: Disable data status read back (default)
1: Enable data status read back
Pace and ECG Data Read Back Registers
Table 57. DATA_STATUS: ECG and Pace Data Ready Status
Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x30 E3_DRDY E2_DRDY E1_DRDY P3_DRDY P2_DRDY P1_DRDY ALARMB 0
[7] E3_DRDY Channel 3 ECG data ready
1: Channel 3 ECG data ready
[6] E2_DRDY Channel 2 ECG data ready
1: Channel 2 ECG data ready
[5] E1_DRDY Channel 1 ECG data ready
1: Channel 1 ECG data ready
[4 ] P3_DRDY Channel 3 pace data ready
1: Channel 3 pace data ready
[3] P2_DRDY Channel 2 pace data ready
1: Channel 2 pace data ready
[2] P1_DRDY Channel 1 pace data ready
1: Channel 1 pace data ready
[1] ALARMB ALARMB status
1: Alarm active (ALARMB output pin driven low)
[0] Reserved —
0
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