Datasheet

ADS1293
SNAS602B –FEBRUARY 2013–REVISED MARCH 2013 www.ti.com
Table 51. DRDYB_SRC: Data Ready Pin Source
Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x27 DRDYB_SRC
[7:6] RESERVED —
[6:0] DRDYB_SRC Select channel to drive the DRDYB pin
000000: DRDYB pin not asserted (default)
000001: Driven by channel 1 pace
000010: Driven by channel 2 pace
000100: Driven by channel 3 pace
001000: Driven by channel 1 ECG
010000: Driven by channel 2 ECG
100000: Driven by channel 3 ECG
Table 52. SYNCB_CN: SYNCB In/Out Pin Control
Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x28 DIS_SYNCB SYNCB_SRC
OUT
[7] RESERVED —
[6] DIS_SYNCBOUT Disable the SYNCB pin output driver
0: Driver enabled and pin configured as output
1: Driver disabled and pin configured as input (default)
Note: Bit should be set to 1 for slave devices.
[5:0] SYNCB_SRC Select channel to drive the SYNCB pin
000000: No source selected (default)
000001: Driven by channel 1 pace
000010: Driven by channel 2 pace
000100: Driven by channel 3 pace
001000: Driven by channel 1 ECG
010000: Driven by channel 2 ECG
100000: Driven by channel 3 ECG
Note: Choose the slowest pace or ECG channel as source. Bits[5:0] must be cleared to 0 for slave
devices.
Table 53. MASK_DRDYB: Optional Mask Control for DRDYB Output
Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x29 DRDYB DRDYB
MASK_CTL1 MASK_CTL0
[7:2] RESERVED —
[1] DRDYBMASK_CTL1 START_CON mask control for DRDYB output
0: DRDYB signal is masked when START_CON is set (default)
1: Disable initial DRDYB masking when START_CON is set
[0] DRDYBMASK_CTL0 Optional mask control for DRDYB output
0: DRDYB signal is masked after out of sync is detected (default)
1: Disable DRDYB masking after out of sync is detected
Note: If an ECG channel is enabled, DRDYB is masked during 6 ECG output data periods.
If all ECG channels are disabled, DRDYB is masked during 6 or 11 pace output data periods, for 1x pace or 2x pace mode respectively.
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