Datasheet

ADS1293
SNAS602B –FEBRUARY 2013–REVISED MARCH 2013 www.ti.com
Digital Registers
Table 44. DIGO_STRENGTH: Digital Output Drive Strength
Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x1F DIGO_STRENGTH
[7:2] RESERVED —
[1:0] DIGO_STRENGTH Digital Output Drive Strength
00: Low drive mode
01: Mid-low drive mode
10: Mid-high drive mode
11: High drive mode (Default)
Table 45. R2_RATE: R2 Decimation Rate
Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x21 R2_RATE
[7:4] RESERVED —
[3:0] R2_RATE R2 decimation rate
0001: 4
0010: 5
0100: 6
1000: 8 (default)
Note: The register sets to its default value if none or more than one bit are enabled.
Table 46. R3_RATE_CH1: R3 Decimation Rate for Channel 1
Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x22 R3_RATE_CH1
[7:0] R3_RATE_CH1 R3 decimation rate for channel 1
00000001: 4
00000010: 6
00000100: 8
00001000: 12
00010000: 16
00100000: 32
01000000: 64
10000000: 128 (default)
Note: The register sets to its default value if none or more than one bit are enabled.
Table 47. R3_RATE_CH2: R3 Decimation Rate for Channel 2
Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x23 R3_RATE_CH2
[7:0] R3_RATE_CH2 R3 decimation rate for channel 2
00000001: 4
00000010: 6
00000100: 8
00001000: 12
00010000: 16
00100000: 32
01000000: 64
10000000: 128 (default)
Note: The register sets to its default value if none or more than one bit are enabled.
64 Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ADS1293