Datasheet

ADS1293

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SNAS602B –FEBRUARY 2013–REVISED MARCH 2013

Table 36. AFE_PACE_CN: Analog Pace Channel Output Routing Control

Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

0x17 PACE2RLDI PACE2WCT SHDN_PACE

[7:3] RESERVED —

[2] PACE2RLDIN Connect the analog pace channel output to RLDIN pin

0: Analog pace channel output is disconnected from the RLDIN pin (default)

1: Connect the analog pace channel output to the RLDIN pin.

Note: The right leg drive amplifier is disconnected from the RLDIN pin and connected internally to the

RLDREF pin when this bit is 1.

[1 ] PACE2WCT Connect the analog pace channel output to WCT pin

0: Analog pace channel output is disconnected from the WCT pin (default)

1: Connect the analog pace channel output to the WCT pin.

Note: The Wilson reference output is disconnected from the WCT pin when this bit is 1. The Wilson

output can be connected internally to IN6 pin with the WILSON_CN register.

[0] SHDN_PACE Shut down analog pace channel

0: Analog pace channel is powered up

1: Analog pace channel is shut down (default)

Error Status Registers

Table 37. ERROR_LOD: Lead Off Detect Error Status

Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

0x18 OUT_LOD

[7:6] RESERVED —

[5:0] OUT_LOD Lead Off Detect Status

There is one bit available per input pin, where the MSB corresponds to input pin IN6 and the LSB

corresponds to input pin IN1.

1: Indicates a lead off error detected on the corresponding input pin.

Note: The clock to digital (internal or external) must be enabled in 0x12[2] for this error register to update.

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