Datasheet

ADS1293

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SNAS602B –FEBRUARY 2013–REVISED MARCH 2013

OSC Control Registers

Table 32. OSC_CN: Clock Source and Output Clock Control

Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

0x12 STRTCLK SHDN_OSC EN_CLKOUT

[7:3] RESERVED —

[2] STRTCLK Start the clock

0: Clock to digital disabled (default)

1: Enable clock to digital

Note: Set this bit high only after the oscillator has started up or after the oscillator has shut down and

the external clock has started up.

[1] SHDN_OSC Select clock source

0: Use internal clock with external crystal on XTAL1 and XTAL2 pins (default)

1: Shut down internal oscillator and use external clock from CLK pin

Note: STRTCLK bit should be low at the time this bit is reconfigured.

[0] EN_CLKOUT Enable CLK pin output driver

0: Clock output driver disabled (default)

1: Clock output driver enabled

AFE Control Registers

Table 33. AFE_RES: Analog Front-End Frequency and Resolution

Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

0x13 FS_HIGH_ FS_HIGH_ FS_HIGH_ EN_HIRES_ EN_HIRES_ EN_HIRES_

CH3 CH2 CH1 CH3 CH2 CH1

[7:6] RESERVED —

[5] FS_HIGH_CH3 Clock frequency for channel 3

0: 102400Hz (default)

1: 204800Hz

[4 ] FS_HIGH_CH2 Clock frequency for channel 2

0: 102400Hz (default)

1: 204800Hz

[3] FS_HIGH_CH1 Clock frequency for channel 1

0: 102400Hz (default)

1: 204800Hz

[2] EN_HIRES_CH3 High resolution mode for channel 3 instrumentation amplifier

0: Disabled (default)

1: Enabled

[1] EN_HIRES_CH2 High resolution mode for channel 2 instrumentation amplifier

0: Disabled (default)

1: Enabled

[0] EN_HIRES_CH1 High resolution mode for channel 1 instrumentation amplifier

0: Disabled (default)

1: Enabled

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