Datasheet

ADS1293

SNAS602B –FEBRUARY 2013–REVISED MARCH 2013

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Table 22. LOD_CURRENT: Lead-Off Detect Current

Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

0x08 CUR_LOD

[7:0] CUR_LOD Lead-off detect current select

The lead-off detect current is programmable in a range of 2.04μA with steps of 8nA.

00000000: 0.000 μA (default)

00000001: 0.008 μA

. .

11111110: 2.032 μA

11111111: 2.040 μA

Table 23. LOD_AC_CN: AC Lead-Off Detect Control

Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

0x09 ACDIV_ ACDIV_LOD

FACTOR

[7] ACDIV_FACTOR AC lead off test frequency division factor

0: Clock divider factor K = 1 (default)

1: Clock divider factor K = 16

[6:0] ACDIV_LOD Clock divider ratiio for AC lead off

There are 7 bits available to program the clock divider that generates the AC lead off test frequency.

Common-Mode Detection and Right Leg Drive Common-Mode Feedback Control Registers

Table 24. CMDET_EN: Common-Mode Detect Enable

Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

0x0A CMDET_ CMDET_ CMDET_ CMDET_ CMDET_ CMDET_

EN_IN6 EN_IN5 EN_IN4 EN_IN3 EN_IN2 EN_IN1

[7:6] RESERVED —

[5:0] CMDET_EN_INx Common-mode detect input enable

There is one bit available per input pin, where the MSB corresponds to input pin IN6 and the LSB

corresponds to input pin IN1.

0: Disable (default)

1: Enable the corresponding pin's voltage to contribute to the average voltage of the common-mode

detect block.

Table 25. CMDET_CN: Common-Mode Detect Control

Addr BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

0x0B CMDET_BW CMDET_CAPDRIVE

[7:6] RESERVED —

[2] CMDET_BW Common-mode detect bandwidth mode

0: Low bandwidth mode (default)

1: High bandwidth mode

[1:0] CMDET_CAPDRIVE Common-mode detect capacitive load drive capability

00: Low cap-drive mode (default)

01: Medium low cap-drive mode

10: Medium high cap-drive mode

11: High cap-drive mode

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