Datasheet

ADS1293

SNAS602B –FEBRUARY 2013–REVISED MARCH 2013

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Simultaneous ECG and PACE Data Read

Each of the three digital channels of the ADS1293 provides a high-performance path for ECG monitoring and a

lower resolution path for monitoring of pace-maker signals. The digitized signals from these two paths can be

read simultaneously from the Pace and ECG Data Read Back Registers.

The ECG signal path achieves higher resolution than the PACE signal path by having one extra filtering stage

(as shown in Figure 18). Due to the difference in filtering stages of the two paths, the PACE data is available for

reading at a much higher rate than the ECG data. In this sense, the PACE channel must be selected as the

driving source of the DRDYB signal.

In the Streaming mode, the data from the DATA_LOOP register should be read after the DRDYB line is asserted;

this means that new data is available. In order to read both ECG and PACE data from the DATA_LOOP register,

the channels of interest must be enabled in the CH_CNFG register.

As an example, the 3-Lead ECG Application can be reconfigured to perform simultaneous ECG and PACE data

reads from channel 1:

1. Set address 0x00 = 0x00: Stops data conversion (if any).

2. Set address 0x2F = 0x32: Enables channel 1 PACE, channel 1 ECG, and channel 2 ECG for loop.

read-back mode

3. Set address 0x27 = 0x01: Reconfigures the DRDYB source to channel 1 PACE .

4. Set address 0x00 = 0x01: Starts data conversion.

In this case, new PACE data from channel 1 is available on every DRDYB assertion; ECG data from channel

1 and channel 2, on the other hand, is available every six DRDYB assertions (R3_RATE_CH1 =

R3_RATE_CH2 = 6).

There are different approaches for handling simultaneous ECG and PACE data read. One approach is to

read ECG data every time that PACE data is ready, over-sampling the ECG channel. This is possible

because old conversion values are retained in the data registers until new data overwrites them.

A second approach is to also read the DATA_STATUS register. Continuing from the steps above:

5. Set address 0x00 = 0x00: Stops data conversion.

6. Set address 0x2F = 0x33: Enables data ready status, channel 1 PACE, channel 1 ECG, and channel 2.

ECG for loop read-back mode

7. Set address 0x00 = 0x01: Starts data conversion.

The DATA_STATUS register indicates the channel(s) that are updated at a given DRDYB assertion; this

information can potentially be used to discard irrelevant data.

A third and more complex approach is to continuously reprogram the CH_CNFG register based on the contents

of DATA_STATUS register. The CH_CNFG register should be reprogrammed to read PACE+ECG data only

when the DATA_STATUS register indicates ECG data is available. After reading the PACE+ECG data, the

CH_CNFG register should be reprogrammed back to reading only the DATA_STATUS register and the PACE

data. In this case, the ECG data is not oversampled and the SPI communication can be significantly reduced for

cases where a decimation rate, R3_RATE_CHx, is large. The reconfiguration of the CH_CNFG register should

be done before the next DRDYB assertion to avoid losing data.

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