Datasheet
ADS1293
www.ti.com
SNAS602B –FEBRUARY 2013–REVISED MARCH 2013
8- or 12-Lead ECG Application
Figure 34 shows the ADS1293 master/slave setup for an 8-Lead to 12-Lead ECG system. The ADS1293 uses
the Common-Mode Detector to measure the common-mode of the patient’s body by averaging the voltage of
input pins IN1, IN2 and IN3, and uses this signal in the right leg drive feedback circuit
(3)
. The output of the RLD
amplifier is connected to the right leg electrode to drive the common-mode of the patient’s body. The Wilson
Central Terminal is generated by the ADS1293 and is used as a reference to measure the chest electrodes, V1-
V6; it is strongly recommended to shield the external Wilson connections, which due to the high output
impedance of the Wilson reference, is prone to pick up external interference. The master ADS1293 generates a
synchronization pulse on the SYNCB pin (configured as an output). This drives the SYNCB pins (configured as
inputs) of the two slave ADS1293. The master chip uses an external 4.096MHz crystal oscillator connected
between the XTAL1 and XTAL2 pins to create the clock sources for the device and outputs this clock on the CLK
pin.
The next steps will configure the master device; it is assumed that the device registers contain their default
power-up values.
1. Set address 0x01 = 0x11: Connects channel 1’s INP to IN2 and INN to IN1.
2. Set address 0x02 = 0x19: Connect channel 2’s INP to IN3 and INN to IN1.
3. Set address 0x0A = 0x07: Enables the common-mode detector on input pins IN1, IN2 and IN3.
4. Set address 0x0C = 0x04: Connects the output of the RLD amplifier internally to pin IN4.
5. Set addresses 0x0D = 0x01, 0x0E = 0x02, 0x0F = 0x03: Connects the first buffer of the Wilson reference to
the IN1 pin, the second buffer to the IN2 pin, and the third buffer to the IN3 pin.
6. Set address 0x12 = 0x05: Uses external crystal, feeds the output of the internal oscillator module to the
digital, and enables the CLK pin output driver
7. Set address 0x14 = 0x24: Shuts down unused channel 3’s signal path.
8. Set address 0x21 = 0x02: Configures the R2 decimation rate as 5 for all channels.
9. Set address 0x22 = 0x02: Configures the R3 decimation rate as 6 for channel 1.
10. Set address 0x23 = 0x02: Configures the R3 decimation rate as 6 for channel 2.
11. Set address 0x27 = 0x08: Configures the data-ready source to channel 1 ECG (or fastest channel).
12. Set address 0x28 = 0x08: Configures the synchronization source to channel 1 ECG (or slowest channel).
13. Set address 0x2F = 0x30: Enables ECG channel 1 and ECG channel 2 for loop read-back mode.
Next, configure the slave devices; it is assumed that the device registers contain their default power-up
values. In this example, both devices will have the same configuration; therefore, they can potentially be
configured in parallel by asserting the CSB signal of both chips.
14. Set address 0x01 = 0x0C: Connects channel 1’s INP to IN1 and INN to IN4.
15. Set address 0x02 = 0x14: Connects channel 2’s INP to IN2 and INN to IN4.
16. Set address 0x03 = 0x1C: Connects channel 3’s INP to IN3 and INN to IN4.
17. Set address 0x12 = 0x06: Uses external clock signal on the CLK pin and feeds it to the digital.
18. Set address 0x21 = 0x02: Configures the R2 decimation rate as 5 for all channels.
19. Set address 0x22 = 0x02: Configures the R3 decimation rate as 6 for channel 1.
20. Set address 0x23 = 0x02: Configures the R3 decimation rate as 6 for channel 2.
21. Set address 0x24 = 0x02: Configures the R3 decimation rate as 6 for channel 3.
22. Set address 0x27 = 0x00: DRDYB pin not asserted by slave devices.
23. Set address 0x28 = 0x40: Disables SYNCB driver and configures pin as input.
24. Set address 0x2F = 0x70: Enables ECG channel 1, ECG channel 2, and ECG channel 3 for loop read-back
mode.
(3) The ideal values of R
1
, R
2
and C
1
will vary per system/application; typical values for these components are: R
1
= 100kΩ, R
2
= 1MΩ and
C
1
= 1.5nF.
Copyright © 2013, Texas Instruments Incorporated 43
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