Datasheet

ADS1293

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SNAS602B –FEBRUARY 2013–REVISED MARCH 2013

reset, but it will return to a logic 1 if the internal alarm condition persists. After being filtered the alarms are all

routed to a digital logic block that detects whether a new alarm has occurred. If this happens, the appropriate bit

in the ERROR_STATUS register will be set and the ALARMB pin will be pulled down. The bits in the

ERROR_STATUS register will be reset and the ALARMB pin will released when the ERROR_STATUS register is

read.

Figure 31. Graphical Illustration of Alarm Propagation

Reference Voltage Generators

The common-mode and right leg drive reference generates VDD/2.2 volts, which are present on the RLDREF

pin. This reference is used as an internal common-mode reference, as the reference for the analog pace

channel, and should be powered on at all times when a sigma-delta modulator is running. It can be powered

down by programming bit SHDN_CMREF=1 in the REF_CN register. The RLDREF pin should have a 0.1µF

bypass capacitor to ground.

The internal reference, V

REF

, generates 2.4V, which are present on the CVREF pin. The CVREF pin must have a

1µF bypass capacitor to ground with low ESR and is not designed to be loaded with other circuitry. This

reference should also be powered on at all times when a sigma-delta modulator is running. It can be powered

down programming bit SHDN_REF=1 in the REF_CN register. It is possible to provide the reference voltage

externally on this pin when the internal reference generator is shut down.

All three voltage generators require a somewhat larger start up time compared to the other circuit blocks inside

the ADS1293, which is why they are treated differently in the global power down or standby states, as will be

described in the next section.

Product Folder Links: ADS1293