Datasheet

ADS1293
www.ti.com SNAS602B –FEBRUARY 2013–REVISED MARCH 2013
Single-Chip Multi-Channel Synchronization
The filter channels are synchronized when DRDYB assertion is at a fixed frequency and new data from each
source is available at some integer multiple of DRDYB. This synchronization mode requires that the fastest
output data source is selected to drive DRDYB in the DRDYB_SRC register.
The filter channels will start synchronized if the output data rates in all channels are the same or integer multiples
of each other. Synchronization between channels will be continuously enforced as long as the slowest output
source is selected as the synchronization source in the SYNCB_CN register. The SYNCB pin output driver can
be disabled in a single-chip system, regardless of the synchronization source selected, and synchronization will
continue to be enforced between channels. The SYNCB output driver is disabled programming bit
DIS_SYNCBOUT=1 in the SYNCB_CN register.
Multi-Chip Synchronization
Synchronization in a multiple ADS1293 system is achieved when all the devices share a common clock and
synchronization source. The common clock source, f
OSC
, can be driven from the CLK pin of an ADS1293 when
its CLK pin output driver is enabled in the OSC_CN register. The common synchronization source can be driven
from the SYNCB pin of the device with the slowest data rate in the system. An ADS1293 is configured as a
synchronization source by enabling its SYNCB output driver and selecting the slowest data rate channel to drive
the line in the SYNCB_CN register. The SYNCB_CN register of the other devices should be programmed to 0x40
to configure their SYNCB pins as inputs. When configured as an output, SYNCB is driven on the falling edge of
f
OSC
and when configured as an input, SYNCB is sampled on the rising edge of f
OSC
.
Synchronization Errors
Detected synchronization events are reported to the ERROR_SYNC register. A phase error is generated when
the phase of divided clocks of the timing generator has been adjusted to comply with the SYNCB input signal. A
timing error is generated when the timing of the indicated channel has been updated to comply with the timing of
the synchronization source, internal or external. By default, a synchronization error will propagate to the
ALARMB output pin. Reporting of a synchronization error can be disabled in the MASK_ERR register.
Alarm Functions
The ADS1293 has multiple warning flags to diagnose possible fault conditions in the ECG monitoring application.
The warning flags can be read in the Error Status Registers . The system errors are filtered by the digital circuitry
(see Error Filtering), and for this reason, the master clock must be active for the alarms to be reflected in the
error registers.
1. ERROR_LOD: Indicates which input has a lead-off error. The lead-off detection was described in Lead-Off
Detection (LOD) .
2. ERROR_STATUS: Contains the following error flags:
– SYNCEDGEERR: This flag is raised when a synchronization error occurs, as described in
Synchronization Errors.
– CH3ERR: This flag is raised when one of the 5 LSBs or bit 6 of the ERROR_RANGE3 register is a logic
1. It indicates an out-of-range condition at the AFE in channel 3. These error conditions are described in
Instrumentation Amplifier Fault Detection and in Sigma-Delta Modulator Fault Detection .
– CH2ERR: See above, but for channel 2.
– CH1ERR: See above, but for channel 1.
– LEADOFF: This error flag is raised when one of the OUT_LOD bits in the ERROR_LOD register is a
logic 1.
– BATLOW: This error flag is raised when the supply voltage of the ADS1293 drops below 2.7V. This can
be used as a warning sign to the microcontroller that the state of charge of a supply battery is almost
below levels of operation. The ADS1293 is designed to function within specification for supplies larger
than 2.7V but communication the digital communication interface will work down to 2.4V so that this alarm
condition can still be communicated to the microcontroller. A low battery error propagates to the ALARMB
pin unless the MASK_BATLOW bit in the MASK_ERR register is set to 1. System alarms are filtered by
the digital circuitry (see Error Filtering), and for this reason, the master clock must be active in order to
capture an alarm.There is also a battery voltage monitoring feature that can be used to monitor the state
of charge of the battery during normal operation described in Battery Monitoring.
– RLDRAIL: This error flag is raised when the output voltage of the right leg drive amplifier is approaching
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