Datasheet

ADS1293

SNAS602B –FEBRUARY 2013–REVISED MARCH 2013

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Data Ready Bar

Data ready bar (DRDYB) is an active low output signal and is asserted when new data is ready to be read. After

DRDYB is asserted and an SPI read of ECG or PACE data occurs, DRDYB will be deasserted at the 14th rising

edge of SCLK.

Figure 29. DRDYB Behavior for a Complete Read Operation

New data is available regardless of the serial interface being ready to read the data or not, and therefore, the

data is lost if it is not read before the next DRDYB assertion. If DRDYB is asserted and the data is not read,

DRDYB is automatically deasserted at least t

DRDYB

seconds before the next DRDYB assertion. The value for

DRDYB

can be found in the TIMING DIAGRAMS.

Figure 30. DRDYB Behavior for an Incomplete Read Operation

The source channel driving the assertion of the DRDYB signal can be configured in the DRDYB_SRC register. In

order to see the DRDYB output pin asserted, one bit of this register must be set to 1 to select the digital channel

to drive it. Multiple channels should not be selected to drive the DRDYB output pin, otherwise, it will result in

unexpected behavior. The selected channel should not be shut down in the AFE_SHDN_CN register, and if the

source is an ECG channel, its filter should not be disabled in the DIS_EFILTER register. It is strongly

recommended to select the channel with the fastest data rate as the source for the DRDYB signal to avoid loss

of data.

By default, the DRDYB signal is masked during the first few data samples after the start of a conversion or when

a synchronization error is detected. If any ECG channel is enabled, DRDYB is masked during the first six data

samples of the slowest enabled ECG channel. If all ECG channels are disabled, DRDYB is masked for the first

six data samples of the slowest enabled pace channel when the data rate is 1xODR, and for the first eleven data

samples of the slowest enabled pace channel when the data rate is 2xODR. Masking can be disabled in the

MASK_DRDYB register.

Synchronization

There are three filter timing generators implemented to support independent filter settings. Under normal

conditions, the filters always start synchronized when the START_CON bit in the CONFIG register is set to 1,

and will remain synchronized. Synchronization can also be continually enforced for the eventuality of a channel

losing synchronization, and it can be used in single-chip and multiple-chip systems.

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