Datasheet

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SNAS602B –FEBRUARY 2013–REVISED MARCH 2013

Each assertion of chip select bar (CSB) starts a new register access. The R/Wb bit in the command field

configures the direction of the access operation; a value of 0 indicates a write operation and a value of 1

indicates a read operation. All output data is driven on the falling edge of the serial clock (SCLK), and for the 16-

bit protocol, SDO read data is driven on the falling edge of clocks 8 through 15. All input data on the serial data

in (SDI) pin is sampled on the rising edge of SCLK and is written into the register on the rising edge of the 16th

clock. The user is required to deassert CSB after the 16th clock; if CSB is deasserted before the 16th clock, no

data write will occur.

Random Register Access Protocol

The 16-bit protocol is useful for random address access. CSB must be asserted during 16 clock cycles of SCLK.

Auto-incrementing Address

An access cycle may be extended to multiple registers by simply keeping the CSB asserted beyond the stated

16 clocks of the standard 16-bit protocol. In this mode, CSB must be asserted during 8*(1+N) clock cycles of

SCLK, where N is the amount of bytes to write or read during the access cycle. The auto-incrementing address

mode is useful to access a block of registers of incrementing addresses.

For example, to read the pace and ECG data registers located from address 0x30 to address 0x3F and worth 16

bytes of data, follow the next steps:

1. Execute a read command to address 0x30.

2. Extend the CSB assertion during 136 clock cycles (8+8*16).

During an auto-incrementing read access, SDO outputs the register contents every 8 clock cycles after the initial

8 clocks of the command field. During an auto-incrementing write access, the data is written to the registers

every 8 clock cycles after the initial 8 clocks of the command field.

Automatic address increment stops at address 0x4F for both write and read operations.

Streaming

A read access cycle can operate in streaming mode, also referred to as loop read back mode, by performing a

read operation from the DATA_LOOP register and extending the CSB assertion beyond the standard 16 clocks.

The streaming mode is supported for the DATA_STATUS, DATA_CH1_PACE, DATA_CH2_PACE,

DATA_CH3_PACE, DATA_CH1_ECG, DATA_CH2_ECG and DATA_CH3_ECG registers described in Pace and

ECG Data Read Back Registers. The streaming mode is useful to access the block of pace and ECG data

registers when not all data needs to be read. The channels to read in this mode are selected in the CH_CNFG

enabled in CH_CNFG . The source for pace data is 2 bytes long; the source for ECG data is 3 bytes long, and

the source for data status is 1 byte long.

For example, to read the DATA_STATUS, DATA_CH3_PACE and DATA_CH3_ECG registers located at address