Datasheet

ADS1293

SNAS602B –FEBRUARY 2013–REVISED MARCH 2013

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Table 12. Clock Oscillator Configuration Bits

SHDN_OS EN_CLKO

STRTCLK CLOCK PROPAGATION

C UT

0 X X No clock

1 0 0 Internal clock to digital circuitry

1 0 1 Internal clock to digital circuitry and CLK pin

1 1 X External clock to digital circuitry

Serial Digital Interface

A serial peripheral interface (SPI) allows access to the control registers of the ADS1293. The serial interface is a

generic 4-wire synchronous interface compatible with SPI type interfaces used on many microcontrollers and

DSP controllers.

Digital Output Drive Strength

The strength of the transistors driving the serial data out pin (SDO) can be programmed to four levels in the

DIGO_STRENGTH register. The drive strength will affect the slope of the digital output signal edges, and the

optimal drive strength will depend on the capacitive loading on the SDO pin, where larger capacitive loads

require larger drive strength. The output drive strength configurability may help reduce interference from the SPI

communication into the AFE signal path. In this sense, it is advised to use the lowest drive strength that works

for a particular system.

SPI Protocol

A typical serial interface access cycle is exactly 16 bits long, which includes an 8-bit command field (R/WB + 7-

bit address) to provide for a maximum of 128 direct access addresses, and an 8-bit data field. Figure 28 shows

the access protocol used by this interface. Extended access cycles are possible and they are described in the

Auto-incrementing Address and Streaming sections.

Figure 28. Serial Interface Protocol

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