Datasheet

÷10
SHDN_OSC
STRTCLK
EN_CLKOUT
4.096 MHz
XTAL2
CLK
crystal
oscillator
enable
to internal clock
generators
enable
VDD
VDD
XTAL1
22 pF 22 pF
SHDN_OSC
409.6 kHz
ADS1293
www.ti.com SNAS602B –FEBRUARY 2013–REVISED MARCH 2013
Clock Oscillator
The ADS1293 is designed to operate from a 409.6kHz clock. This clock can be generated by an on-chip crystal
oscillator or provided externally on the bidirectional CLK. The high-accuracy low-power on-chip crystal oscillator
will work with an external 4.096MHz crystal connected between the XTAL1 and XTAL2 pins, each of which must
be loaded with a 20pF capacitor to get an accurate oscillation frequency. The output frequency of the on-chip
crystal oscillator is divided by 10 to generate the required 409.6kHz clock frequency as shown in Figure 27.
Figure 27. Block Diagram of the Clock
Even though the required oscillation frequency of the external crystal is rated at 4.096MHz, both the oscillator
and the chip can tolerate a wider crystal oscillation frequency (3.7MHz to 4.5MHz). Note though that the output
data rate and bandwidth of the SINC filters given in Table 5 through Table 8 will scale according to the crystal
oscillation frequency.
When the internal clock is used, the generated clock can be brought off chip through the CLK pin. Its output
driver is enabled by configuring bit EN_CLKOUT = 1 in the OSC_CN register, allowing a multi-chip system to
operate synchronously from a single crystal oscillator. Setting bit STRTCLK = 1 allows the internal 409.6kHz
clock to propagate to the digital circuitry and to the output driver of the CLK pin.
The internal crystal oscillator can be shut down to save power or when the clock of the device is provided
externally. Configuring bit SHDN_OSC = 1 powers down the internal crystal oscillator and enables the input
driver of the CLK pin. The external clock should have a frequency of 409.6kHz with a duty cycle of 50% to get
the SINC filter bandwidth given in Table 5 through Table 8. The chip can tolerate a wider frequency range and
clock duty cycle on this pin (see the External Clock Frequency and the External Clock Duty Cycle parameters in
the Clock section of the ELECTRICAL CHARACTERISTICS table) in exchange of scaling up or down the
bandwidth of the SINC filters. Setting bit STRTCLK = 1 allows the external 409.6kHz clock to propagate to the
digital circuitry.
The STRTCLK bit is designed to ensure all critical blocks of the chip get a clean clock start. The clock source
should first be configured and allowed to start up using the SHDN_OSC and EN_CLKOUT bits, and
subsequently, the STRTCLK bit can be set high.
The oscillator control register bits are summarized in Table 12. In a multi-chip system, the CLK pins of the master
and slaves should be connected together. The master should be configured to generate a clock on the CLK pin
while the slaves should use the CLK pin as a clock input source.
Copyright © 2013, Texas Instruments Incorporated 31
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