Datasheet

ADS1293
www.ti.com SNAS602B –FEBRUARY 2013–REVISED MARCH 2013
The negative input terminal of the RLD op-amp is always connected to the RLDINV pin. By default, the positive
input terminal of the RLD op-amp is routed to the RLDIN pin. However, when bit PACE2RLDIN = 1 in the
AFE_PACE_CN register, the positive input terminal is routed to the internally to the RLD reference. This will
allow connecting the output of the analog pace instrumentation amplifier to the RLDIN pin. The output of the RLD
op-amp is always connected to the RLDOUT pin, and in addition, can be connected to one of the IN1-IN6
terminals by programming the SELRLD bit in the RLD_CN register. The RLD circuit can be shut down in the
same register by setting bit SHDN_RLD = 1.
Capacitive Load Driving
The bandwidth and capacitive load driving capability of the RLD can be configured in the RLD_CN register to
achieve an optimal tradeoff of power consumption. Table 11 lists the power consumption corresponding to
different configuration scenarios.
Table 11. Typical Right Leg Drive Bandwidth, Capacitive Drive, and Power Consumption
GBW C
LOAD
RLD I
SUPPLY
RLD_BW RLD_CAPDRIVE
(kHz) (nF) (µA)
0: Low BW mode 00: Low Cap Drive 50 2 20
0: Low BW mode 01: Medium Low Cap Drive 50 3.3 25
0: Low BW mode 10: Medium High Cap Drive 50 4.5 36
0: Low BW mode 11: High Cap Drive 50 8 55
1: High BW mode 00: Low Cap Drive 200 0.4 23
1: High BW mode 01: Medium Low Cap Drive 200 0.65 29
1: High BW mode 10: Medium High Cap Drive 200 1 39
1: High BW mode 11: High Cap Drive 200 1.6 60
Error Status: RLD Rail
The RLD amplifier incorporates a near to rail alarm function that is triggered when the output of the op-amp is
below 0.2V or above VDD-0.2V. The alarm is reported to the RLDRAIL bit in the ERROR_STATUS register and
indicates that the RLD's feedback loop has difficulty maintaining a constant voltage on the patient’s body. In this
case, the common-mode on the patient’s body may drift away from its target value, but it may still be within the
proper input common-mode voltage range of the ADS1293, and the ECG signal data acquisition can continue.
When the common-mode on the patient’s body is outside the operation range of the ADS1293, the CMOR error
will be raised, as described in the previous section. System alarms are filtered by the digital circuitry (see Error
Filtering) , and for this reason, the master clock must be active in order to capture an alarm.
Lead-Off Detection (LOD)
The lead-off detect (LOD) block of the ADS1293 can be used to monitor the connectivity of the 6 input pins to
electrodes. The LOD block injects a programmable DC or AC excitation current into selected input pins and
detects the voltages that appear on the input pins in response to that current. If a lead is not making a proper
contact, then the electrode impedance will be high, and as a result, the voltage in response to a small test
current will be relatively large, while the voltage for a well-connected lead will be small.
The LOD block can work in one of the three following modes: 1) DC lead-off detect, 2) analog AC lead-off detect
or 3) digital AC lead-off detect. All three LOD modes use a common DAC that provides a programmable
reference current. This reference current is used to set the magnitude of the test current for lead-off detection.
The amplitude of the excitation current used for lead-off detection can be programmed in the LOD_CURRENT
register, where codes 0 to 255 result in currents ranging from 0 to 2.040µA in steps of 8nA.
The complete LOD block can be shut down by programming the SHDN_LOD bit to 1 in the LOD_CN register.
DC Lead-Off Detect
The LOD block can be configured for DC LOD mode by programming a 0 in the SELAC_LOD bit of the LOD_CN
register. In the DC LOD mode, a DC test current can be injected into any of the six input pins by setting the
corresponding bit EN_LOD[x] of the LOD_EN register. Programming a bit to 1 in this register enables a switch
that allows a copy of the current programmed into the DAC to be injected into the desired input pins, as shown in
the simplified block diagram of Figure 23.
Copyright © 2013, Texas Instruments Incorporated 27
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