Datasheet

INP INM
OUT MAX
REF
3.5 V V
1
ADC ADC
2 V 2
é ù
-
= +
ê ú
ë û
S
PACE
f
ODR
R1 R2
=
S
ECG
f
ODR
R1 R2 R3
=
ADS1293
www.ti.com SNAS602B –FEBRUARY 2013–REVISED MARCH 2013
Table 5, Table 6, Table 7, and Table 8 illustrate how these decimation rates R1, R2, and R3 affect the ODR, BW,
and RMS Noise of the PACE and ECG signals. In addition, the ODR and BW also depend on whether the SDM
is running at a low (102.4kHz) or high (204.8kHz) clock frequency (set by the FS_HIGH_CHx bits in the
AFE_RES register). The RMS Noise of the PACE and ECG channels also depend on whether the
instrumentation amplifier is running in low power or high resolution mode (set by the EN_HIRES bits in the
AFE_RES register).
In summary, the output data rate of an ECG channel can be calculated as follows:
(5)
And the output data rate of a PACE channel can be calculated as follows:
(6)
Where f
S
is the clock frequency of the modulator: 102.4kHz, or 204.8kHz.
Filter Settling Time
The low-pass filter frequency responses of the ECG and Pace SINC filters result in a settling time associated
with their outputs as a response to a step input signal. This settling time is determined by the order of the filter,
N, its differential delay, M, and the channel output data rate, ODR:
t
s
= N × M / ODR (7)
The ODR of the filter is a function of the sigma-delta's sampling frequency, f
S
, and the filter decimation rates. The
value of the ODR can be calculated using Equation 5 and Equation 6. For an ECG channel, the value of NxM =
5. For a Pace channel NxM = 5 when operated in the Standard Pace Data Rate (R1 = 4), and NxM = 10 when
operated in the Double Pace Data Rate (R1 = 2).
As a result, an unclamped pace signal applied to the filter input results in an ECG channel minimum settling time
of:
t
S-ECG
= 5 × R1 × R2 × R3 / f
S
(8)
A Standard Pace Data Rate operated Pace channel will go through a minimum settling time of:
t
S-PACE
= 5 × R1 × R2 /f
S
(9)
And a Double Pace Data Rate operated Pace channel will go through a minimum settling time of:
t
S-PACE
= 10 × R1 × R2 / f
S
(10)
Ouput Code (ADC
OUT
)
The ADC
OUT
of the ADS1293 is due to a differential voltage applied between the positive and negative input
terminals of the instrumentation amplifier and can be calculated with Equation 11:
(11)
The reference voltage V
REF
, equals to 2.4V if the on-chip voltage reference is used. ADC
MAX
represents the
maximum output code of the ADC, which corresponds to a theoretical 2.4V signal at the input of the SDM. The
value of ADC
MAX
changes with the configuration of the digital filters, and the corresponding value can be found in
Table 5, Table 6, Table 7, and Table 8. Note that ADC
OUT
equals ADC
MAX
/2 for a 0V differential input.
Copyright © 2013, Texas Instruments Incorporated 17
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