Datasheet

ADS1293

SNAS602B –FEBRUARY 2013–REVISED MARCH 2013

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The 102.4kHz or 204.8kHz clock frequency can be selected for each channel individually by programming the

FS_HIGH_CHx bits in the AFE_RES register.

The SDM also features dithering to reduce tones in the system, a known by-product of Sigma-Delta converters.

The dithering circuit is active by default and is automatically turned OFF when the input signal is larger than

40mV.

Sigma-Delta Modulator Fault Detection

The state of the integrators in the Sigma-Delta Modulator (SDM) are monitored to detect over-range signals that

cause the SDM to become unstable. When an over-range event is detected in the SDM, the state of its

integrators is reset, and the over-range error is reported to the SDM_OR_CHx bits of the ERROR_RANGE1,

ERROR_RANGE2 and ERROR_RANGE3 registers.

Programmable Digital Filters

A programmable digital filter behind the Sigma-Delta Modulator (SDM) reconstructs the signal from the SDM

output bit stream. The filter consist of three programmable SINC filters as shown in Figure 18. Each stage is a

fifth order SINC filter.

Figure 18. SINC Filters

The decimation rates (R1, R2, and R3) of the SINC filters are programmable as described in Table 4. Each of

the three stages further filters and decimates the bit stream so that the output data rate (ODR) and bandwidth

(BW) of the signal is reduced, and at the same time, the resolution is enhanced. A 16-bit digital signal with

relatively high ODR and BW, but with somewhat limited resolution, is available after the second stage; this signal

can be used for PACE pulse detection. That signal is further decimated by the third stage and results in a very

high resolution filtered 24-bit digital signal that is an accurate representation of the ECG signal.

Table 4. Programmable Digital Filter Coefficients

Stage 1 (R1) Stage 2 (R2) Stage 3 (R3)

4 (Standard PACE Data Rate), 2 (Double PACE Data Rate) 4, 5, 6, 8 4, 6, 8, 12, 16, 32, 64, 128

The first stage sets the Standard PACE Data Rate (where the decimation rate R1 = 4) or the Double PACE Data

Rate (where R1 = 2). Operating the device in the Double PACE Data Rate will double the ODR for the first stage

(and therefore also for the subsequent stages). However, the BW of the first stage does not change in this mode;

only the ODR is affected. By operating the device in the Double PACE Data Rate, the ODR of the PACE data is

doubled, and thus, more accurate PACE pulse detection is possible. However, operating the device in the

Double PACE Data Rate will increase its power consumption. The R1 decimation rate can be programmed for

each of the three channels separately by using the R1_RATE register.

Programming the second stage (R2) to a low decimation rate sets a relatively high ODR and BW, but doing so

will also increase the noise level. For digital PACE pulse detection, smalle values for R2 are recommended. The

R2 decimation rate can be programmed using the R2_RATE register.

As the third stage decimation (R3) increases, the ODR and BW of the ECG decreases. When detecting an ECG

signal, higher values of R3 are recommended. The R3 decimation rate for each channel can be individually

programmed using the R3_RATE_CH1, R3_RATE_CH2, and R3_RATE_CH3 registers.

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