ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 ADS1293 Low Power, 3-Channel, 24-Bit Analog Front End for Biopotential Measurements Check for Samples: ADS1293 FEATURES DESCRIPTION • The ADS1293 incorporates all features commonly required in portable, low-power medical, sports, and fitness electrocardiogram (ECG) applications.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Batt.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 CONNECTION DIAGRAM 28-PIN LLP (TOP VIEW) Table 2. Pin Descriptions PIN TYPE NO.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications. VALUE MIN ESD Tolerance (2) MAX UNIT Human Body Model (HBM) For input pins only 1000 V Charge Device Model (CDM) 500 V Analog Supply Voltage, VDD –0.3 6.0 V Digital Supply Voltage, VDDIO –0.3 6.0 V Voltage on any Input Pin –0.3 to (VDD + 0.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 ELECTRICAL CHARACTERISTICS (1) Unless otherwise noted, all limits are specified at TA = +25°C, +2.7V ≤ VDD ≤ +5.5V, +1.65V ≤ VDDIO ≤ MIN(+3.6V, VDD), VREF = +2.4V, fOSC = 409.6kHz, 1µF low ESR capacitor between CVREF and GND, 0.1µF capacitor between RLDREF and GND. Boldface limits apply for TMIN ≤ TA ≤ TMAX. TYP (3) MAX (2) 5.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS(1) (continued) Unless otherwise noted, all limits are specified at TA = +25°C, +2.7V ≤ VDD ≤ +5.5V, +1.65V ≤ VDDIO ≤ MIN(+3.6V, VDD), VREF = +2.4V, fOSC = 409.6kHz, 1µF low ESR capacitor between CVREF and GND, 0.1µF capacitor between RLDREF and GND. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 ELECTRICAL CHARACTERISTICS(1) (continued) Unless otherwise noted, all limits are specified at TA = +25°C, +2.7V ≤ VDD ≤ +5.5V, +1.65V ≤ VDDIO ≤ MIN(+3.6V, VDD), VREF = +2.4V, fOSC = 409.6kHz, 1µF low ESR capacitor between CVREF and GND, 0.1µF capacitor between RLDREF and GND. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS(1) (continued) Unless otherwise noted, all limits are specified at TA = +25°C, +2.7V ≤ VDD ≤ +5.5V, +1.65V ≤ VDDIO ≤ MIN(+3.6V, VDD), VREF = +2.4V, fOSC = 409.6kHz, 1µF low ESR capacitor between CVREF and GND, 0.1µF capacitor between RLDREF and GND. Boldface limits apply for TMIN ≤ TA ≤ TMAX. PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT ANALOG PACE CHANNEL BW Gain 3.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 TIMING DIAGRAMS Unless otherwise noted, all limits specified at TA = 25°C, +2.7V ≤ VDD ≤ +5.5V, +1.65 ≤ VDDIO ≤ MIN(+3.6V, VDD), VREF = +2.4V, fOSC = 409.6kHz and a 10pF capacitive load in parallel with a 10kΩ load on SDO. Figure 1. Write Timing Diagram PARAMETER CONDITIONS MIN TYP MAX UNIT 20 MHz FSCLK Serial Clock Frequency tPH SCLK Pulse Width - High FSCLK = 20MHz 0.4/FSCLK tPL SCLK Pulse Width - Low FSCLK = 20MHz 0.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS All plots at TA = +25°C, VDD = +3.3V, VDDIO = +1.8V, VSS = VSSIO = 0V, internal VREF = +2.4V, VCM = RLDREF, internal fOSC = 409.6kHz, data rate = 1067sps, and High-Resolution mode, unless otherwise noted. VOS vs VDD VOS vs VCM 30 Input-Referred Offset Voltage (µV) Input-Referred Offset Voltage (µV) 30 25 20 15 10 5 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 TA = +25°C TA = -20°C 20 15 10 TA = +85°C 5 0 0.25 5.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 TYPICAL CHARACTERISTICS (continued) All plots at TA = +25°C, VDD = +3.3V, VDDIO = +1.8V, VSS = VSSIO = 0V, internal VREF = +2.4V, VCM = RLDREF, internal fOSC = 409.6kHz, data rate = 1067sps, and High-Resolution mode, unless otherwise noted. IBIAS vs VCM IBIAS vs VCM 140 1.00 TA = +25°C 0.95 Input Bias Current (nA) 100 TA = -20°C 80 60 40 0.90 0.85 0.80 0.75 20 0.70 TA = +85°C VIN DIFF = ±400mV VIN DIFF = ±400mV 0 0.95 1.15 1.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots at TA = +25°C, VDD = +3.3V, VDDIO = +1.8V, VSS = VSSIO = 0V, internal VREF = +2.4V, VCM = RLDREF, internal fOSC = 409.6kHz, data rate = 1067sps, and High-Resolution mode, unless otherwise noted. FFT PLOT ECG CHANNEL (50Hz Signal) FFT PLOT PACE CHANNEL (50Hz Signal) 0 0 Data Rate = 1067SPS ECG BW = 215Hz VDDIO = +3.3V -20 -40 Amplitude (dBFS) Amplitude (dBFS) -40 Data Rate = 25.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 FUNCTIONAL DESCRIPTION The ADS1293 is a fully integrated signal chain for ECG applications. It features three low-power, 24-bit resolution channels for ECG and pace monitoring and an auxiliary fourth channel for analog pace detection. In addition, the ADS1293 features AC and DC lead-off detection, right leg drive capability, and Wilson and Goldberger terminals.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Table 3.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Analog Front End The ADS1293 contains three analog front ends that convert a differential analog voltage into a digital signal. Each analog front end consists of an instrumentation amplifier (INA), a sigma-delta modulator (SDM), and a digital filter.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com The 102.4kHz or 204.8kHz clock frequency can be selected for each channel individually by programming the FS_HIGH_CHx bits in the AFE_RES register. The SDM also features dithering to reduce tones in the system, a known by-product of Sigma-Delta converters. The dithering circuit is active by default and is automatically turned OFF when the input signal is larger than 40mV.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Table 5, Table 6, Table 7, and Table 8 illustrate how these decimation rates R1, R2, and R3 affect the ODR, BW, and RMS Noise of the PACE and ECG signals. In addition, the ODR and BW also depend on whether the SDM is running at a low (102.4kHz) or high (204.8kHz) clock frequency (set by the FS_HIGH_CHx bits in the AFE_RES register).
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Output Data Rate, Bandiwdth and Noise Tables Table 5. Channel Parameters with SDM Running at 102.4kHz and at Standard PACE Data Rate (R1 = 4) (1) PACE CHANNEL R2 4 5 6 8 (1) R3 RMS NOISE ADCMAX BW [Hz] LOW POWER [µV] HIGH RES [µV] 4 0x800000 1600 325 4.47 4.16 6 0xF30000 1067 215 3.42 3.05 8 0x800000 800 160 2.92 2.57 12 0xF30000 533 105 2.37 2.07 0x800000 400 80 2.06 1.81 32 0x800000 200 40 1.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Table 6. Channel Parameters with SDM Running at 102.4kHz and at Double PACE Data Rate (R1 = 2) (1) PACE CHANNEL R2 4 5 6 8 (1) R3 RMS NOISE ADCMAX BW [Hz] LOW POWER [µV] HIGH RES [µV] 4 0x800000 3200 640 38.17 37.92 6 0xF30000 2133 430 7.04 6.72 8 0x800000 1600 320 4.35 3.93 0xF30000 1067 215 3.40 3.02 0x800000 800 160 2.92 2.57 32 0x800000 400 80 2.08 1.79 64 0x800000 200 40 1.49 1.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Table 7. Channel Parameters with SDM Running at 204.8kHz and at Standard PACE Data Rate (R1 = 4) (1) PACE CHANNEL R2 4 5 6 8 (1) R3 RMS NOISE ADCMAX BW [Hz] LOW POWER [µV] HIGH RES [µV] 4 0x800000 3200 640 5.20 4.59 6 0xF30000 2133 430 3.92 3.38 8 0x800000 1600 325 3.32 2.86 0xF30000 1067 215 2.69 2.31 0x800000 800 160 2.34 1.99 32 0x800000 400 80 1.68 1.43 64 0x800000 200 40 1.25 1.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Table 8. Channel Parameters with SDM Running at 204.8kHz and at Double PACE Data Rate (R1 = 2) (1) PACE CHANNEL R2 4 5 6 8 (1) R3 RMS NOISE ADCMAX BW [Hz] LOW POWER [µV] HIGH RES [µV] 4 0x800000 6400 1280 41.27 40.81 6 0xF30000 4267 850 7.79 7.32 8 0x800000 3200 640 4.97 4.35 0xF30000 2133 430 3.88 3.36 0x800000 1600 325 3.32 2.85 32 0x800000 800 160 2.34 1.98 64 0x800000 400 80 1.69 1.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Analog Pace Channel The ADS1293 features an additional analog pace channel to process pulses from a pace maker. The analog pace channel is suitable for low power applications where the device can be configured for low data rates in ECG mode only, while an analog channel detects PACE pulses.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Wilson Reference The ADS1293 features a Wilson reference block consisting of three buffer amplifiers and resistors that can generate the voltages for the Wilson Central Terminal or Goldberger terminals. Each of the three buffer amplifiers can be connected to any input pin, IN1 through IN6, by programming the WILSON_EN1, WILSON_EN2, and WILSON_EN3 registers. A buffer that is not connected to an input pin is automatically disabled.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com The output of Wilson Central Terminal generated by the ADS1293, as seen in Figure 20, is defined as: WCTOUT = (BUF1 + BUF2 + BUF3)/3 The user could program the WILSON_EN1 register to connect the RA electrode to BUF1, program the WILSON_EN2 register to connect the LA electrode to BUF2, and program the WILSON_EN3 register to connect the LL electrode to BUF3.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Common-Mode (CM) Detector The Common-Mode Detector averages the voltage of up to six input pins. Its output can be used in a right leg drive feedback circuit. The selection of the input pins that contribute to the average is configured in the CMDET_EN register. The Common-Mode Detector is automatically disabled when no input pin is selected. Figure 21.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Table 10. Typical Common-Mode Detector Bandwidth, Capacitive Drive and Power Consumption CMDET_BW CMDET_CAPDRIVE BW (kHz) CLOAD (nF) CMDET ISUPPLY (µA) 0: Low BW mode 00: Low Cap Drive 50 2 39 0: Low BW mode 01: Medium Low Cap Drive 50 3.3 45 0: Low BW mode 10: Medium High Cap Drive 50 4.5 56 0: Low BW mode 11: High Cap Drive 50 8 75 1: High BW mode 00: Low Cap Drive 150 0.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 The negative input terminal of the RLD op-amp is always connected to the RLDINV pin. By default, the positive input terminal of the RLD op-amp is routed to the RLDIN pin. However, when bit PACE2RLDIN = 1 in the AFE_PACE_CN register, the positive input terminal is routed to the internally to the RLD reference. This will allow connecting the output of the analog pace instrumentation amplifier to the RLDIN pin.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Figure 23. Simplified DC Lead-off Detect Block Diagram For the selected input pins, a Schmitt-trigger comparator then compares the voltage that appears on the pin to (VDD-0.5V). The result of this comparison can be accessed through the corresponding OUT_LOD[x] bit of the ERROR_LOD register. If a lead is off, then the injected current has no return path to ground, and as a result, the voltage on the associated input pin will rise towards VDD.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 1 Threshold Voltage (V) Level 4 Level 3 Level 2 0.1 Level 1 0.01 500 1k 2k 3k 4k 5k Excitation Frequency (Hz) 10k C01 Figure 24. Analog AC Lead-Off Reference Levels The comparator outputs can be accessed at the OUT_LOD[x] bit of the ERROR_LOD register. A high comparator output signal indicates that the AC voltage at the excitation frequency is larger than the programmed threshold, which indicates that the lead is not well connected.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com This AC voltage will be digitized by the AFE, and the result is available in the digital AFE output signals. The lead connectivity can be determined in the digital domain by applying an FFT to the digital data and by measuring the amplitude of the tone at the AC LOD excitation frequency.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Clock Oscillator The ADS1293 is designed to operate from a 409.6kHz clock. This clock can be generated by an on-chip crystal oscillator or provided externally on the bidirectional CLK. The high-accuracy low-power on-chip crystal oscillator will work with an external 4.096MHz crystal connected between the XTAL1 and XTAL2 pins, each of which must be loaded with a 20pF capacitor to get an accurate oscillation frequency.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Table 12. Clock Oscillator Configuration Bits STRTCLK SHDN_OS C EN_CLKO UT 0 X X No clock 1 0 0 Internal clock to digital circuitry 1 0 1 Internal clock to digital circuitry and CLK pin 1 1 X External clock to digital circuitry CLOCK PROPAGATION Serial Digital Interface A serial peripheral interface (SPI) allows access to the control registers of the ADS1293.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Each assertion of chip select bar (CSB) starts a new register access. The R/Wb bit in the command field configures the direction of the access operation; a value of 0 indicates a write operation and a value of 1 indicates a read operation. All output data is driven on the falling edge of the serial clock (SCLK), and for the 16bit protocol, SDO read data is driven on the falling edge of clocks 8 through 15.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Data Ready Bar Data ready bar (DRDYB) is an active low output signal and is asserted when new data is ready to be read. After DRDYB is asserted and an SPI read of ECG or PACE data occurs, DRDYB will be deasserted at the 14th rising edge of SCLK. Figure 29.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Single-Chip Multi-Channel Synchronization The filter channels are synchronized when DRDYB assertion is at a fixed frequency and new data from each source is available at some integer multiple of DRDYB. This synchronization mode requires that the fastest output data source is selected to drive DRDYB in the DRDYB_SRC register.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com the supply rails. The flag goes high when the output voltage of the common-mode detector is 200mV away from either supply rail. This condition would occur if the common-mode on the patient’s body is far away from the target value and as a result the right leg drive amplifier needs to deliver a lot of charge to the patient’s body to restore the common-mode voltage.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 reset, but it will return to a logic 1 if the internal alarm condition persists. After being filtered the alarms are all routed to a digital logic block that detects whether a new alarm has occurred. If this happens, the appropriate bit in the ERROR_STATUS register will be set and the ALARMB pin will be pulled down. The bits in the ERROR_STATUS register will be reset and the ALARMB pin will released when the ERROR_STATUS register is read.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Power Management The ADS1293 has many features that allow the optimization of power consumption. The common-mode detector and right leg drive amplifier can be configured to achieve the optimum AC performance to power consumption ratio in a given application environment. Almost all internal circuit blocks can be powered down to reduce power consumption.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 APPLICATION INFORMATION Example Applications 3-Lead ECG Application A 3-Lead ECG system can be implemented using two channels as shown in Figure 32. In this example, the right arm (RA), left arm (LA), left leg (LL) and right leg (RL) are connected to the IN1, IN2, IN3 and IN4 pins respectively.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com 6. Set address 0x14 = 0x24: Shuts down unused channel 3’s signal path. 7. Set address 0x21 = 0x02: Configures the R2 decimation rate as 5 for all channels. 8. Set address 0x22 = 0x02: Configures the R3 decimation rate as 6 for channel 1. 9. Set address 0x23 = 0x02: Configures the R3 decimation rate as 6 for channel 2. 10. Set address 0x27 = 0x08: Configures the DRDYB source to channel 1 ECG (or fastest channel). 11.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 5-Lead ECG Application Figure 33 shows the ADS1293 in a 5-Lead ECG system setup. Similar to the 3-Lead application, the ADS1293 uses the Common-Mode Detector to measure the common-mode of the patient’s body by averaging the voltage of input pins IN1, IN2 and IN3, and uses this signal in the right leg drive feedback circuit (2).
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com 8. Set address 0x12 = 0x04: Uses external crystal and feeds the output of the internal oscillator module to the digital. 9. Set address 0x21 = 0x02: Configures the R2 decimation rate as 5 for all channels. 10. Set address 0x22 = 0x02: Configures the R3 decimation rate as 6 for channel 1. 11. Set address 0x23 = 0x02: Configures the R3 decimation rate as 6 for channel 2. 12.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 8- or 12-Lead ECG Application Figure 34 shows the ADS1293 master/slave setup for an 8-Lead to 12-Lead ECG system. The ADS1293 uses the Common-Mode Detector to measure the common-mode of the patient’s body by averaging the voltage of input pins IN1, IN2 and IN3, and uses this signal in the right leg drive feedback circuit (3).
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Finally, start the conversion. This should be written to all three chips. 25. Set address 0x00 = 0x01: Starts data conversion (repeat this step for every device). The three devices will run synchronously using the SYNCB signal. Follow the description in the Streaming section to read the data. The ADS1293 measures lead I, lead II and leads V1-V6.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 5V 3.3V XTAL2 1M RSTB CVREF VSS VDD 0.1 PF 5V 22 pF 5V 1 PF 22 pF 3.3V 4.096 MHz XTAL1 VDDIO www.ti.com 0.1 PF CLK IN1 IN2 + CH1 InA - ¨ Modulator Digital Filter + CH2 InA - ¨ Modulator Digital Filter I DRDYB V4 V5 V6 IN5 IN6 WILSON_EN CMDET_EN Wilson ref. CM detect WCT RLD Amp. SDI SCLK CSB ALARMB 3.3V VDDIO 3.3V 1 PF VSSIO 0.1 PF SYNCB R2 R1 RSTB CVREF VSS 0.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Simultaneous ECG and PACE Data Read Each of the three digital channels of the ADS1293 provides a high-performance path for ECG monitoring and a lower resolution path for monitoring of pace-maker signals. The digitized signals from these two paths can be read simultaneously from the Pace and ECG Data Read Back Registers.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 REGISTERS 1. If written to, RESERVED bits must be written to 0 unless otherwise indicated. 2. Read back value of RESERVED bits and registers is unspecified and should be discarded. 3. Recommended values must be programmed and forbidden values must not be programmed where they are indicated in order to avoid unexpected results. 4.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 REGISTER NAME www.ti.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Operation Mode Registers Table 14.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Table 16.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Table 18.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Lead-Off Detect Control Registers Table 20.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Table 21. LOD_EN: Lead-Off Detect Enable Addr 0x07 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 EN_LOD [7:6] RESERVED — [5] EN_LOD_6 DC or Analog AC Lead-off-Detection: These bits enable the lead-off-detection for input IN6. 0: Lead-off detection disabled (default) 1: Lead-off detection enabled Digital AC Lead-off-Detection: These bits configure the phase of the current injected into channel CH3.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Table 22. LOD_CURRENT: Lead-Off Detect Current Addr 0x08 [7:0] BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 CUR_LOD CUR_LOD Lead-off detect current select The lead-off detect current is programmable in a range of 2.04μA with steps of 8nA. 00000000: 0.000 μA (default) 00000001: 0.008 μA .. .. 11111110: 2.032 μA 11111111: 2.040 μA Table 23.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Table 26.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Table 29.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 OSC Control Registers Table 32. OSC_CN: Clock Source and Output Clock Control Addr 0x12 [7:3] BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 STRTCLK BIT1 SHDN_OSC BIT0 EN_CLKOUT RESERVED — [2] STRTCLK Start the clock 0: Clock to digital disabled (default) 1: Enable clock to digital Note: Set this bit high only after the oscillator has started up or after the oscillator has shut down and the external clock has started up.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Table 34.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Table 36. AFE_PACE_CN: Analog Pace Channel Output Routing Control Addr 0x17 BIT7 BIT6 RESERVED — [2] PACE2RLDIN Connect the analog pace channel output to RLDIN pin 0: Analog pace channel output is disconnected from the RLDIN pin (default) 1: Connect the analog pace channel output to the RLDIN pin. Note: The right leg drive amplifier is disconnected from the RLDIN pin and connected internally to the RLDREF pin when this bit is 1.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Table 38.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Table 40.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Table 41.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Table 42.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Digital Registers Table 44. DIGO_STRENGTH: Digital Output Drive Strength Addr 0x1F BIT7 BIT6 BIT5 BIT4 [7:2] RESERVED — [1:0] DIGO_STRENGTH Digital Output Drive Strength 00: Low drive mode 01: Mid-low drive mode 10: Mid-high drive mode 11: High drive mode (Default) BIT3 BIT2 BIT1 BIT0 DIGO_STRENGTH Table 45.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Table 48. R3_RATE_CH3: R3 Decimation Rate for Channel 3 Addr 0x24 [7:0] BIT7 BIT6 R3_RATE_CH3 BIT5 BIT4 BIT3 R3_RATE_CH3 BIT2 BIT1 BIT0 R3 decimation rate for channel 3 00000001: 4 00000010: 6 00000100: 8 00001000: 12 00010000: 16 00100000: 32 01000000: 64 10000000: 128 (default) Note: The register sets to its default value if none or more than one bit are enabled. Table 49.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Table 51.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Table 54.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Table 56.
ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 Table 58.
ADS1293 SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 www.ti.com Table 62.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS1293CISQ/NOPB WQFN RSG 28 ADS1293CISQE/NOPB WQFN RSG ADS1293CISQX/NOPB WQFN RSG SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 28 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 28 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1293CISQ/NOPB WQFN RSG 28 1000 213.0 191.0 55.0 ADS1293CISQE/NOPB WQFN RSG 28 250 213.0 191.0 55.0 ADS1293CISQX/NOPB WQFN RSG 28 4500 367.0 367.0 35.
MECHANICAL DATA RSG0028A SQA28A (Rev B) www.ti.
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