Datasheet

ADS1291
ADS1292
ADS1292R
SBAS502B DECEMBER 2011REVISED SEPTEMBER 2012
www.ti.com
CONFIG1: Configuration Register 1
Address = 01h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SINGLE_SHOT 0 0 0 0 DR2 DR1 DR0
This register configures each ADC channel sample rate.
Bit 7 SINGLE_SHOT: Single-shot conversion
This bit sets the conversion mode
0 = Continuous conversion mode (default)
1 = Single-shot mode
Bits[6:3] Must be set to '0'
Bits[2:0] DR[2:0]: Channel oversampling ratio
These bits determine the oversampling ratio of both channel 1 and channel 2.
BIT OVERSAMPLING RATIO DATA RATE
(1)
000 f
MOD
/ 1024 125 SPS
001 f
MOD
/ 512 250 SPS
010 f
MOD
/ 256 500 SPS (default)
011 f
MOD
/ 128 1 kSPS
100 f
MOD
/ 64 2 kSPS
101 f
MOD
/ 32 4 kSPS
110 f
MOD
/ 16 8 kSPS
111 Do not use Do not use
(1) f
CLK
= 512 kHz and CLK_DIV = 0 or f
CLK
= 2.048 MHz and CLK_DIV = 1.
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