Datasheet

START Opcode
START Pin
DIN
4 / f
CLK
DRDY
or
t
DR
t
SETTLE
ADS1291
ADS1292
ADS1292R
www.ti.com SBAS502B –DECEMBER 2011–REVISED SEPTEMBER 2012
START
The START pin must be set high or the START command sent to begin conversions. When START is low or if
the START command has not been sent, the device does not issue a DRDY signal (conversions are halted).
When using the START opcode to control conversion, hold the START pin low. The ADS1291, ADS1292, and
ADS1292R feature two modes to control conversion: continuous mode and single-shot mode. The mode is
selected by SINGLE_SHOT (bit 7 of the CONFIG1 register). In multiple device configurations the START pin is
used to synchronize devices (see the Multiple Device Configuration subsection of the SPI Interface section for
more details).
Settling Time
The settling time (t
SETTLE
) is the time it takes for the converter to output fully settled data when the START signal
is pulled high. Once START is pulled high, DRDY is also pulled high. The next DRDY falling edge indicates that
data are ready. Figure 37 shows the timing diagram and Table 11 shows the settling time for different data rates.
The settling time depends on f
CLK
and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1
register). Refer to Table 10 for the settling time as a function of t
MOD
. Note that when START is held high and
there is a step change in the input signal, it takes 3 t
DR
for the filter to settle to the new value. Settled data are
available on the fourth DRDY pulse. Settling time number uncertainty is one t
MOD
cycle. Therefore, it is
recommended to add one t
MOD
cycle delay before issuing SCLK to retrieve data.
(1) Settling time uncertainty is one t
MOD
cycle.
Figure 37. Settling Time
Table 11. Settling Time for Different Data Rates
DR[2:0] SETTLING TIME
(1)
UNIT
(2)
000 4100 t
MOD
001 2052 t
MOD
010 1028 t
MOD
011 516 t
MOD
100 260 t
MOD
101 132 t
MOD
110 68 t
MOD
111 — —
(1) Settling time uncertainty is one t
MOD
cycle.
(2) t
MOD
= 4 t
CLK
for CLK_DIV = 0 and t
MOD
= 16 t
CLK
for CLK_DIV = 1.
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