Datasheet

1
CS
SCLK
DIN
DOUT
2
3 8
1 2
83
t
CSSC
t
DIST
t
DIHD
t
CSH
t
DOPD
t
SPWH
t
SPWL
t
SCCS
Hi-Z
t
CSDOZ
t
CSDOD
Hi-Z
t
SCLK
t
SDECODE
CLK
t
CLK
ADS1291
ADS1292
ADS1292R
SBAS502B DECEMBER 2011REVISED SEPTEMBER 2012
www.ti.com
TIMING CHARACTERISTICS
NOTE: SPI settings are CPOL = 0 and CPHA = 1.
Figure 1. Serial Interface Timing
Timing Requirements For Figure 1
(1)
2.7 V DVDD 3.6 V 1.7 V DVDD 2 V
PARAMETER DESCRIPTION MIN TYP MAX MIN TYP MAX UNIT
Master clock period (CLK_DIV bit of LOFF_STAT register = 0) 1775 2170 1775 2170 ns
t
CLK
Master clock period (CLK_DIV bit of LOFF_STAT register = 1) 444 542 444 542 ns
t
CSSC
CS low to first SCLK, setup time 6 17 ns
t
SCLK
SCLK period 50 66.6 ns
t
SPWH, L
SCLK pulse width, high and low 15 25 ns
t
DIST
DIN valid to SCLK falling edge: setup time 10 10 ns
t
DIHD
Valid DIN after SCLK falling edge: hold time 10 11 ns
t
DOPD
SCLK rising edge to DOUT valid 12 22 ns
t
CSH
CS high pulse 2 2 t
CLKs
t
CSDOD
CS low to DOUT driven 10 20 ns
t
SCCS
Eighth SCLK falling edge to CS high 3 3 t
CLKs
t
SDECODE
Command decode time 4 4 t
CLKs
t
CSDOZ
CS high to DOUT Hi-Z 10 20 ns
(1) Specifications apply from –40°C to +85°C. Load on D
OUT
= 20 pF || 100 kΩ.
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