Datasheet

2
®
ADS1286
SPECIFICATIONS
At T
A
= T
MIN
to T
MAX
, +V
CC
= +5V, V
REF
= +5V, f
SAMPLE
= 12.5kHz, , f
CLK
= 16 • f
SAMPLE
, unless otherwise specified.
TIMING CHARACTERISTICS
f
CLK
= 200kHz, T
A
= T
MIN
to T
MAX
.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
SMPL
Analog Input Sample Time See Operating Sequence 1.5 2.0 Clk Cycles
t
SMPL (MAX)
Maximum Sampling Frequency ADS1286 20 kHz
t
CONV
Conversion Time See Operating Sequence 12 Clk Cycles
t
dDO
Delay TIme, DCLOCK to D
OUT
Data Valid See Test Circuits 85 150 ns
t
dis
Delay TIme, CS to D
OUT
Hi-Z See Test Circuits 25 50 ns
t
en
Delay TIme, DCLOCK to D
OUT
Enable See Test Circuits 50 100 ns
t
hDO
Output Data Remains Valid After DCLOCK C
LOAD
= 100pF 15 30 ns
t
f
D
OUT
Fall Time See Test Circuits 70 100 ns
t
r
D
OUT
Rise Time See Test Circuits 60 100 ns
t
CSD
Delay Time, CS to DCLOCK See Operating Sequence 0 ns
t
SUCS
Delay Time, CS to DCLOCK See Operating Sequence 30 ns
ADS1286, ADS1286A ADS1286K, ADS1286B ADS1286C, ADS1286L
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
ANALOG INPUT
Full-Scale Input Range +In – (–In) 0 V
REF
✻✻✻✻V
Absolute Input Voltage +In –0.2 V
CC
+0.2 ✻✻✻✻V
–In –0.2 +0.2 ✻✻✻✻V
Capacitance 25 ✻✻pF
Leakage Current ±1 ✻✻µA
SYSTEM PERFORMANCE
Resolution 12 ✻✻Bits
No Missing Codes 12 ✻✻Bits
Integral Linearity ±1 ±2 ✻✻ ±0.5 ±1 LSB
Differential Linearity ±0.5 ±1.0 ±0.75 ±0.25 ±0.75 LSB
Offset Error 0.75 ±3 ✻✻ ✻✻LSB
Gain Error ±2 ±8 ✻✻ ✻✻LSB
Noise 50 ✻✻µVrms
Power Supply Rejection 82 ✻✻dB
SAMPLING DYNAMICS
Conversion Time 12 ✻✻
Clk Cycles
Acquisition Time 1.5 ✻✻
Clk Cycles
Small Signal Bandwidth 500 ✻✻kHz
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion V
IN
= 5.0Vp-p at 1kHz –85 ✻✻dB
V
IN
= 5.0Vp-p at 5kHz –83 ✻✻dB
SINAD V
IN
= 5.0Vp-p at 1kHz 72 ✻✻dB
Spurious Free Dynamic Range V
IN
= 5.0Vp-p at 1kHz 90 ✻✻dB
REFERENCE INPUT
REF Input Range 1.25 2.5
V
CC
+0.05V
✻✻✻✻✻✻V
Input Resistance CS = V
CC
5000 ✻✻M
CS = GND, f
CLK
= 0Hz 5000 ✻✻M
Current Drain CS = V
CC
0.01
2.5
✻✻ ✻✻µA
t
CYC
640µs, f
CLK
25kHz
2.4
20
✻✻ ✻✻µA
t
CYC
= 80µs, f
CLK
= 200kHz
2.4
20
✻✻ ✻✻µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS ✻✻
Logic Levels:
V
IH
I
IH
= +5µA3 +V
CC
✻✻✻✻V
V
IL
I
IL
= +5µA 0.0 0.8 ✻✻✻✻V
V
OH
I
OH
= 250µA3 +V
CC
✻✻✻✻V
V
OL
I
OL
= 250µA 0.0 0.4 ✻✻✻✻V
Data Format Straight Binary ✻✻
POWER SUPPLY REQUIREMENTS
Power Supply Voltage
V
CC
+4.50 5 5.25 ✻✻✻✻✻✻V
Quiescent Current, V
ANA
t
CYC
640µS, f
CLK
25kHz
200 400 ✻✻ ✻✻µA
t
CYC
= 90µS, f
CLK
= 200kHz
250 500 ✻✻ ✻✻µA
Power Down CS = V
CC
3 ✻✻µA
TEMPERATURE RANGE
Specified Performance ADS1286, K, L 0 +70 ✻✻✻✻°C
ADS1286A, B, C –40 +85 ✻✻✻✻°C
Specifications same as grade to the left.