Datasheet

RESET
CLKInput
RESET
DOUT
DIN
SCLK
HPF/SYNC
MFLAG
DGND
CLK
20
4
55
4,12,23
2
10
11
1
SYNC
MFLAG1
DRDY
MFLAG2
DVDD
47W
PINMOD
47W
47W
47W
47W
47W
47W
1 Fm
+3.3V
(1)
ADS1281
RESET
DOUT
DIN
SCLK
HPF/SYNC
MFLAG
DGND
CLK
20
4
55
6,12,23
2
10
11
1
DVDD
PINMOD
47W
DRDY
3
47W
47W
1 Fm
+3.3V
(1)
ADS1281
4.096MHzClock
FPGA
22
24
BYPAS
1 Fm
24
BYPAS
1 Fm
DOUT1
DIN1
SCLK1
47W
DOUT2
DIN2
SCLK2
ADS1281
SBAS378D –AUGUST 2007–REVISED JUNE 2010 www.ti.com
Figure 57 shows the digital connection to an FPGA
For best performance, the FPGA and the ADS281s
(field programmable gate array) device. In this
should operate from the same clock. Avoid ringing on
example, two ADS1281s are shown connected. The
the digital inputs. 47Ω resistors in series with the
DRDY output from each ADS1281 can be used;
digital traces can help to reduce ringing by controlling
however, when the devices are synchronized, the
impedances. Place the resistors at the source (driver)
DRDY output from only one device is sufficient. A
end of the trace. Unused digital inputs should not
shared SCLK line between the devices is optional.
float; tie them directly to DVDD or GND.
The modulator over-range flag (MFLAG) from each
device ties to the FPGA. For synchronization, one
SYNC control line connects all ADS1281 devices.
The RESET line also connects to all ADS1281
devices.
NOTE: Dashed lines are optional.
(1) For DVDD < 2.25V, see the DVDD Power Supply section.
Figure 57. FPGA Device
38 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1281