Datasheet

PWDN Pin
DRDY
t
DR
Wakeup
Command
SystemClock
(f )
CLK
DRDY
RESET Pin
RESETCommand
t
RST
Settled
Data
or
t
CRHD
t
DR
t
RCSU
CLK
DVDD
DRDY
InternalReset
1Vnom
AVDD AVSS-
3.5Vnom
2
16
t
DR
f
CLK
ADS1281
SBAS378D –AUGUST 2007–REVISED JUNE 2010 www.ti.com
RESET (RESET Pin and Reset Command) In power-down, note that the device outputs remain
active and the device inputs must not float. When the
The ADS1281 may be reset in two ways: toggle the
Standby command is sent, the SPI port and the
RESET pin low or send a Reset command. When
configuration registers are kept active. Figure 41 and
using the RESET pin, take it low and hold for at least
Table 13 show the timing.
2/f
CLK
to force a reset. The ADS1281 is held in reset
until the pin is released. By command, RESET takes
effect on the next rising edge of f
CLK
after the eighth
rising edge of SCLK of the command. Note: to ensure
that the Reset command can function, the SPI
interface may require a reset; see the Serial Interface
section.
In reset, registers are set to default and the
conversions are synchronized on the next rising edge
of CLK. New conversion data are available, as shown
Figure 41. PWDN Pin and Wake-Up Command
in Figure 40 and Table 12.
Timing
(Table 13 shows t
DR
)
POWER-ON SEQUENCE
The ADS1281 has three power supplies: AVDD,
AVSS, and DVDD. Figure 42 shows the power-on
sequence of the ADS1281. The power supplies can
be sequenced in any order. The supplies [the
difference of (AVDD – AVSS) and DVDD] generate
an internal reset whose outputs are summed to
generate a global internal reset. After the supplies
Figure 40. Reset Timing
have crossed the minimum thresholds, 2
16
f
CLK
cycles
are counted before releasing the internal reset. After
the internal reset is released, new conversion data
Table 12. Reset Timing for Figure 40
are available, as shown in Figure 42 and Table 13.
PARAMETER DESCRIPTION MIN UNITS
t
CRHD
CLK to RESET hold time 10 ns
t
RCSU
RESET to CLK setup time 10 ns
t
RST
RESET low 2 1/f
CLK
62.98046875/
t
DR
Time for data ready
f
DATA
+ 468/f
CLK
POWER-DOWN
(PWDN Pin and Standby Command)
There are two ways to power-down the ADS1281:
take the PWDN pin low or send a Standby command.
When the PWDN pin is pulled low, the internal
Figure 42. Power-On Sequence
circuitry is disabled to minimize power and the
contents of the register settings are reset.
Table 13. Power-On, PWDN Pin, and Wake-Up Command Timing for New Data
PARAMETER DESCRIPTION FILTER MODE
See Appendix, Table 25 SINC
(1)
Time for data ready 2
16
CLK cycles after power-on;
t
DR
and new data ready after PWDN pin or Wake-Up command
62.98046875/f
DATA
+ 468/f
CLK
(2)
FIR
(1) Supply power-on and PWDN pin default is 1000SPS FIR.
(2) Subtract 2 CLK cycles for the Wake-Up command. The Wake-Up command is timed from the next rising edge of CLK to after the eighth
rising edge of SCLK during command to DRDY falling.
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