Datasheet

SystemClock
(f )
CLK
SYNCCommand
SYNCPin
DRDY
(Pulse-Sync)
t
SPWL
NewData
Ready
t
CSHD
t
SPWH
DRDY
(Continuous-Sync)
DOUT
t
DR
t
SCSU
t
DR
NewData
Ready
SystemClock
(f )
CLK
SYNC
DRDY
t
CSHD
t
SCSU
t
SYNC
1/f
DATA
t
SPWH
t
SPWL
ADS1281
www.ti.com SBAS378D –AUGUST 2007–REVISED JUNE 2010
PULSE-SYNC MODE Synchronization occurs on the next rising CLK edge
after the SYNC pin rising edge; or after the eighth
In Pulse-sync mode, the ADS1281 stops and restarts
rising SCLK edge (opcode SYNC). To be effective,
the conversion process when a sync event occurs (by
the SYNC opcode should broadcast simultaneously
pin or command). When the sync event occurs, the
to all ADS1281s.
device resets the internal memory; DRDY goes high,
and after the digital filter has settled, new conversion
data are available, as shown in Figure 38 and
Table 11.
CONTINUOUS-SYNC MODE
In Continuous-sync mode, either a single sync pulse
or a continuous clock may be applied. When a single
sync pulse is applied (rising edge), the device
behaves similar to the Pulse-sync mode. However, in
this mode, DRDY continues to toggle unaffected but
the DOUT output is held low until data are ready.
When the conversion data are non-zero, new
conversion data are ready (as shown in Figure 38).
When a continuous clock is applied to the SYNC pin,
the period must be an integral multiple of the output
Figure 38. Pulse-Sync Timing, Continuous-Sync
data rate or the device re-synchronizes. Note that
Timing with Single Sync
synchronization results in the restarting of the digital
filter and an interruption of 63 readings.
When the sync input is first applied on the first rising
edge of CLK, the device re-synchronizes (under the
condition t
SYNC
≠ N/f
DATA
). DRDY continues to output
but DOUT is held low until the new data are ready.
Then, if the period of the applied sync clock matches
an integral multiple of the output data rate, the device
freely runs without re-synchronization. The phase of
the applied clock and output data rate (DRDY) are
not matched as a result of the initial delay of DRDY
after SYNC is applied. Figure 39 shows the timing for
Continuous-sync mode.
Figure 39. Continuous-Sync Timing with Sync
Clock
Table 11. Pulse-Sync Timing for Figure 38 and Figure 39
PARAMETER DESCRIPTION MIN MAX UNITS
t
SYNC
SYNC period
(1)
1 Infinite n/f
DATA
t
CSHD
CLK to SYNC hold time to not latch on CLK edge 10 ns
t
SCSU
SYNC to CLK setup time to latch on CLK edge 10 ns
t
SPWH, L
SYNC pulse width, high or low 2 1/f
CLK
Time for data ready (SINC filter) See Appendix, Table 25
t
DR
Time for data ready (FIR filter) 62.98046875/f
DATA
+ 468/f
CLK
(1) Continuous-Sync mode; a free-running SYNC clock input without causing re-synchronization.
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