Datasheet

AVSS 300mV<(AINPorAINN)<AVDD+300mV-
ESD
Diodes
ESD
Diodes
11.5pF
R W=85k
(f =1.024MHz)
EFF
MOD
AVDD
AVSS
VREFP
VREFN
R =
EFF
f C´
MOD X
1
AVSS 300mV<(VREFPorVREFN)<AVDD+300mV-
ADS1281
www.ti.com SBAS378D –AUGUST 2007–REVISED JUNE 2010
The charging of the input sampling capacitors draws
a transient current from the source driving the
ADS1281 ADC inputs. The average value of this
current can be used to calculate an effective
impedance (R
EFF
) where R
EFF
= V
IN
/I
AVERAGE
. These
impedances scale inversely with f
MOD
. For example, if
f
MOD
is reduced by a factor of two, the impedances
double.
ESD diodes protect the analog inputs. To keep these
diodes from turning on, make sure the voltages on
the input pins do not go below AVSS by more than
300mV, and likewise do not exceed AVDD by more
than 300mV, as shown in Equation 5.
(5)
Some applications of the device may require external
Figure 37. Simplified Reference Input Circuit
clamp diodes and/or series resistors to limit the input
The ADS1281 reference inputs are protected by ESD
voltage to within this range.
diodes. In order to prevent these diodes from turning
The ADS1281 is a very high-performance ADC. For
on, the voltage on either input must stay within the
optimum performance, it is essential that the
range shown in Equation 6:
ADS1281 inputs be driven with a buffer with noise
and distortion commensurate with the ADS1281
performance; see the Applications section. Most
applications require an external capacitor (C0G/NPO
(6)
dielectric) directly across the input pins. Depending
A high-quality reference voltage is necessary for
on the input driver settling characteristics, some
achieving the best performance from the ADS1281.
experimentation may be necessary to optimize the
Noise and drift on the reference degrade overall
value to minimize THD (generally 10nF). Best
system performance, and it is critical that special care
performance is achieved with the common-mode
be given to the circuitry generating the reference
signal centered at mid-supply.
voltages in order to achieve full performance. For
Although optimized for differential signals, the
most applications, a 1mF ceramic capacitor applied
ADS1281 inputs may be driven with a single-ended
directly to the reference inputs pins is suggested.
signal by fixing one input to mid-supply. To take
advantage of the full dynamic range, the driven input
MASTER CLOCK INPUT (CLK)
should swing 5V
PP
for V
REF
= 5V.
The ADS1281 requires a clock input for operation.
The clock is applied to the CLK pin. The data
VOLTAGE REFERENCE INPUTS
conversion rate scales directly with the CLK
(VREFP, VREFN)
frequency. Power consumption versus CLK frequency
The voltage reference for the ADS1281 ADC is the
is relatively constant (see the Typical Characteristics).
differential voltage between VREFP and VREFN:
As with any high-speed data converter, a high-quality,
V
REF
= VREFP – VREFN. The reference inputs use a
low-jitter clock is essential for optimum performance.
structure similar to that of the analog inputs with the
Crystal clock oscillators are the recommended clock
circuitry on the reference inputs shown in Figure 37.
source. Make sure to avoid excess ringing on the
The average load presented by the switched
clock input; keep the clock trace as short as possible
capacitor reference input can be modeled with an
and use a 50Ω series resistor close to the source.
effective differential impedance of R
EFF
= t
SAMPLE
/C
IN
(t
SAMPLE
= 1/f
MOD
). Note that the effective impedance
of the reference inputs loads an external reference
with non-zero source impedance.
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