Datasheet

0.01 0.1
NormalizedFrequency(f/f )
C
0
-7.5
-15.0
-22.5
-30.0
-45.0
Amplitude(dB)
90
75
60
45
30
15
0
Phase( )°
1 10 100
Phase
Amplitude
-37.5
t
SAMPLE MOD
=1/f
ON
OFF
S
1
S
2
OFF
ON
S
1
S
1
AVSS+2.5V
R =R ||2R
AIN EFFB EFFA
AVSS+2.5V
R =325kW
EFFA
R =61kW
EFFB
(f =1.024MHz)
MOD
R =325kW
EFFA
AINN
AINP
C =3pF
A1
C =16pF
B
C =3pF
A2
S
2
AVSS+2.5V
S
2
AVSS+2.5V
AINN
AINP
Equivalent
Circuit
AVDD
AVSS
R =
EFF
f C´
MOD X
1
ADS1281
SBAS378D –AUGUST 2007–REVISED JUNE 2010 www.ti.com
Figure 34 shows the first-order amplitude and phase
response of the HPF. Note that in the case of
applying step inputs or synchronizing, the settling
time of the filter should be taken into account.
ANALOG INPUT CIRCUITRY (AINP, AINN)
The ADS1281 measures the differential input signal
V
IN
= (AINP – AINN) against the differential reference
V
REF
= (VREFP – VREFN) using internal capacitors
that are continuously charged and discharged.
Figure 36 shows the simplified schematic of the ADC
input circuitry; the right side of the figure illustrates
the input circuitry with the capacitors and switches
replaced by an equivalent circuit. Figure 35
Figure 34. HPF Amplitude and Phase Response
demonstrates the ON/OFF timings for the switches of
Figure 36.
In Figure 36, S
1
switches close during the input
sampling phase. With switch S
1
closed, C
A1
charges
to AINP, C
A2
charges to AINN, and C
B
charges to
(AINP – AINN). For the discharge phase, S
1
opens
first and then S
2
closes. C
A1
and C
A2
discharge to
approximately to AVSS + 2.5V and C
B
discharges to
0V. This two-phase sample/discharge cycle repeats
with a period of t
SAMPLE
= 1/f
MOD
. f
MOD
is the operating
frequency of the modulator. See the Master Clock
Figure 35. S
1
and S
2
Switch Timing for Figure 36
Input (CLK) section.
Figure 36. Simplified ADC Input Structure
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