Datasheet

HPF[dec]=65,536 1 -
cos +sin 1w -
N N
w
cos w
N
1 2-
0 20 40
Frequency(Hz)
35
30
25
20
15
10
5
GroupDelay(1/f )
DATA
60 80 100 120 140 160 180 200
LinearPhaseFilter
MinimumPhaseFilter
GainError(dB)
FrequencyRatio(f /f )
HP DATA
0
-0.10
-0.20
-0.30
-0.40
-0.50
0.0001 0.001
0.01 0.1
ADS1281
www.ti.com SBAS378D –AUGUST 2007–REVISED JUNE 2010
Minimum Phase Response
The minimum phase filter provides a short delay from
the arrival of an input signal to the output, but the
relationship (phase) is not constant versus frequency,
(4)
as shown in Figure 32. The filter phase is selected by
Where:
the PHS bit (Register mode) or the PHS/MCLK pin
HPF = High-pass filter register value (converted
(Pin mode); Table 7 shows additional information.
to hexadecimal)
Table 7. FIR Phase Selection
w
N
= 2pf
HP
/f
DATA
(normalized frequency,
radians)
PHS BIT or
PHS/MCLK PIN FILTER PHASE
f
HP
= High-pass corner frequency (Hz)
0 Linear
f
DATA
= Data rate (Hz)
1 Minimum
Table 8. High-Pass Filter Value Examples
(1)
f
HP
(Hz) DATA RATE (SPS) HPF[1:0]
0.5 250 0337h
1.0 500 0337h
1.0 1000 019Ah
(1) In Pin Control mode the HPF value is fixed at 0332h.
The HPF causes a small gain error, in which case the
magnitude depends on the ratio of f
HP
/f
DATA
. For
many common values of (f
HP
/f
DATA
), the gain error is
negligible. Figure 33 shows the gain error of the HPF.
The gain error factor is illustrated in Equation 11 (see
the Appendix at the end of this document).
Figure 32. FIR Group Delay (f
DATA
= 500Hz)
HPF Stage
The last stage of the ADS1281 filter block is a
first-order HPF implemented as an IIR structure. This
filter stage blocks dc signals and rolls off
low-frequency components below the cut-off
frequency. The transfer function for the filter is shown
in Equation 12 of the Appendix.
The high-pass corner frequency is programmed by
registers HPF[1:0], in hexadecimal. Equation 4 is
used to set the high-pass corner frequency. Table 8
lists example values for the high-pass filter.
Figure 33. HPF Gain Error
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