Datasheet

H(Z)=
1 Z-
-N
N(1 Z- )
-1
5
SincFilter
(Decimateby
8to128)
CoefficientFilter
(FIR)
(Decimateby32)
High-PassFilter
(IIR)
Filter
MUX
ToOutputRegister
FromModulator
DirectModulator
BitStream
30
3
CAL
Block
Code
Clip
31
FilterMode
(RegisterSelect)
ADS1281
SBAS378D –AUGUST 2007–REVISED JUNE 2010 www.ti.com
Table 4. Digital Filter Selection, Pin Mode
DIGITAL FILTER
MOD/DIN HPF/SYNC
The digital filter receives the modulator output and
PIN PIN DIGITAL FILTERS SELECTED
decimates the data stream. By adjusting the amount
1 X Bypass; modulator output mode
of filtering, tradeoffs can be made between resolution
and data rate: filter more for higher resolution, filter 0 0 Sinc + FIR
less for higher data rate.
Sinc + FIR + HPF
0 1
(low-pass and high-pass)
The digital filter is comprised of three cascaded filter
stages: a variable-decimation, fifth-order sinc filter; a
Sinc Filter Stage (sinx/x)
fixed-decimation FIR, low-pass filter (LPF) with
selectable phase; and a programmable, first-order,
The sinc filter is a variable decimation rate, fifth-order,
high-pass filter (HPF), as shown in Figure 25.
low-pass filter. Data are supplied to this section of the
filter from the modulator at the rate of f
MOD
(f
CLK
/4).
The output can be taken from one of the three filter
The sinc filter attenuates the high-frequency noise of
blocks, as shown in Figure 25. To implement the
the modulator, then decimates the data stream into
digital filter completely off-chip, select the filter bypass
parallel data. The decimation rate affects the overall
setting (modulator output). For partial filtering by the
data rate of the converter; it is set by the DR[1:0] and
ADS1281, select the sinc filter output. For complete
MODE selections, as shown in Table 5.
on-chip filtering, activate both the sinc and FIR
stages. The HPF can then be included to remove dc
Equation 2 shows the scaled Z-domain transfer
and low frequencies from the data. Table 3 shows the
function of the sinc filter.
filter options in Register mode. Table 4 shows the
filter options in Pin mode.
Table 3. Digital Filter Selection, Register Mode
FILTR[1:0] BITS DIGITAL FILTERS SELECTED
00 Bypass; modulator output mode
Where:
01 Sinc
N = decimation ratio (2)
10 Sinc + FIR
Sinc + FIR + HPF
11
(low-pass and high-pass)
Figure 25. Digital Filter and Output Code Processing
Table 5. Sinc Filter Data Rates (CLK = 4.096MHz)
DR[1:0] PINS DR[2:0] REGISTER DECIMATION RATIO (N) SINC DATA RATE (SPS)
00 000 128 8,000
01 001 64 16,000
10 010 32 32,000
11 011 16 64,000
— 100 8 128,000
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