Datasheet

MFLAG
+100
(AINP AINN)-
-100
0
V (%ofFull-Scale)
IN
CLK
SYNC
PHS/MCLK
DR0/M0
DR1/M1
t
MCD0, 1
(MCLK=CLK/4)
t
SCSU
t
CSHD
t
CMD
t
SYMD
ADS1281
www.ti.com SBAS378D –AUGUST 2007–REVISED JUNE 2010
FILTR[1:0] = 00. Pins DR0/M0 and DR1/M1 then
become the modulator data outputs and the
PHS/MCLK becomes the modulator clock output.
When not in the modulator mode, these pins are
inputs and must not float.
The modulator output is composed of three signals:
one output for the modulator clock (PHS/MCLK) and
two outputs for the modulator data (DR0/M0 and
DR1/M1). The modulator clock output rate is f
MOD
(f
CLK
/4). Synchronization resets the MODCLK phase,
Figure 23. Modulator Over-Range Flag Operation
as shown in Figure 24. The SYNC input is latched on
the rising edge of CLK. The MODCLK resets and the
next rising edge of MODCLK occurs three CLK
MODULATOR OUTPUT MODE
periods later, as shown in Figure 24.
The modulator digital stream output is available
The modulator output data are two bits wide, which
directly, bypassing and disabling the internal digital
must be merged together before being filtered. Use
filter. The modulator output mode is activated in the
the time domain equation of Equation 1 to merge the
Pin mode by setting MOD/DIN = 1, and in Register
data outputs.
mode by setting the CONFIG0 register bits
Figure 24. Modulator Mode Timing
Table 2. Modulator Output Timing for Figure 24
PARAMETER DESCRIPTION MIN TYP MAX UNIT
t
MCD0, 1
MODCLK rising edge to M0, M1 valid propagation delay
(1)
100 ns
CLK rising edge to MODCLK rising edge reset time after
t
CMD
3 1/f
CLK
synchronization
t
CSHD
CLK to SYNC hold time to not latch on CLK edge 10 ns
t
SCSU
SYNC to CLK setup time to latch on CLK edge 10 ns
t
SYMD
SYNC to stable bit stream 16 1/f
MOD
(1) Load on M0 and M1 = 20pF || 100kΩ.
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