Datasheet

2nd-Order
2nd-Stage
DS
2nd-Order
1st-Stage
DS
AnalogInput(V )
IN
4th-OrderModulator
PHS/MCLK
DR0/M0
DR1/M1
f
CLK
/4
Y[n]=3M0[n 2] 6M0[n 3]+4M0[n 4]
+9(M1[n] 2M1[n 1]+M1[n 2])
- - - -
- - -
ADS1281
www.ti.com SBAS378D –AUGUST 2007–REVISED JUNE 2010
The RESET input resets the register settings ADC
(Register mode) and also restarts the conversion
The ADC block of the ADS1281 is composed of two
process.
blocks: a high-accuracy modulator and a
The PWDN input sets the device into a micro-power programmable digital filter.
state. Note that register settings are not retained in
PWDN mode. Use the STANDBY command in its
MODULATOR
place if it is desired to retain register settings (the
The high-performance modulator is an
quiescent current in the Standby mode is slightly
inherently-stable, fourth-order, ΔΣ, 2 + 2 pipelined
higher).
structure, as shown in Figure 20. It shifts the
Noise-immune Schmitt-trigger and clock-qualified
quantization noise to a higher frequency (out of the
inputs (RESET and SYNC) provide increased
passband) where digital filtering can easily remove it.
reliability in high-noise environments.
The modulator can be filtered either by the on-chip
digital filter or by use of post-processing filters.
The serial interface is used to read conversion data,
in addition to reading from and writing to the
configuration registers.
NOISE PERFORMANCE
The ADS1281 offers outstanding noise performance.
Table 1 summarizes the SNR performance.
Table 1. Noise Performance (Typical)
(1)
DATA RATE FILTER –3dB BW (Hz) SNR (dB)
250 FIR 103 130
500 FIR 206 127
Figure 20. Fourth-Order Modulator
1000 FIR 413 124
2000 FIR 826 121
The modulator first stage converts the analog input
4000 FIR 1652 118
voltage into a pulse-code modulated (PCM) stream.
(1) V
IN
= 20mV
DC
.
When the level of differential analog input (AINP –
AINN) is near one-half the level of the reference
voltage 1/2 × (VREFP – VREFN), the ‘1’ density of
IDLE TONES
the PCM data stream is at its highest. When the level
The ADS1281 modulator incorporates an internal
of the differential analog input is near zero, the PCM
dither signal that randomizes the idle tone energy.
‘0’ and ‘1’ densities are nearly equal. At the two
Low-level idle tones may still be present, typically
extremes of the analog input levels (+FS and –FS),
–137dB below full-scale. The low-level idle tones can
the ‘1’ density of the PCM streams are approximately
be shifted out of the passband with the application of
+90% and +10%, respectively.
an external 20mV offset.
The modulator second stage produces a '1' density
data stream designed to cancel the quantization
noise of the first stage. The data streams of the two
stages are then combined before input to the digital
filter stage, as shown in Equation 1.
(1)
M0[n] represents the most recent first-stage output
while M0[n – 1] is the previous first-stage output.
When the modulator output is enabled, the digital
filter shuts down to save power.
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