ADS1281 AD S 12 81 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 High-Resolution Analog-to-Digital Converter Check for Samples: ADS1281 FEATURES DESCRIPTION • The ADS1281 is an extremely high-performance, single-chip analog-to-digital converter (ADC) designed for the demanding needs of energy exploration and seismic monitoring environments. The single-chip design promotes board area savings for improvements in high-density applications.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 ELECTRICAL CHARACTERISTICS Limit specifications at –40°C to +85°C, typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK VREFN = –2.5V, DVDD = +3.3V, and fDATA = 1000SPS, unless otherwise noted. (1) = 4.096MHz, VREFP = +2.5V, ADS1281 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale input voltage VIN = AINP – AINN Absolute input range AINP or AINN ±VREF/2 AVSS – 0.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Limit specifications at –40°C to +85°C, typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK (1) = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, and fDATA = 1000SPS, unless otherwise noted. ADS1281 PARAMETER CONDITIONS MIN TYP MAX UNIT 0.5 5 (AVDD – AVSS) + 0.2 V V VOLTAGE REFERENCE INPUTS Reference input voltage VREF = VREFP – VREFN Negative reference input VREFN AVSS – 0.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 DEVICE INFORMATION TSSOP-24 Top View CLK 1 24 BYPAS SCLK 2 23 DGND DRDY 3 22 DVDD DOUT 4 21 PINMODE MOD/DIN 5 20 RESET DGND 6 19 PWDN PHS/MCLK 7 18 VREFP DR1/M1 8 17 VREFN DR0/M0 9 16 AVSS HPF/SYNC 10 15 AVDD MFLAG 11 14 AINN DGND 12 13 AINP ADS1281 TERMINAL FUNCTIONS DESCRIPTION NAME NO.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com TIMING DIAGRAM tSCDL tSCLK tSPWH SCLK tDIST tSPWL tSCDL DIN tDIHD tDOHD DOUT tDOPD TIMING REQUIREMENTS At TA = –40°C to +85°C and DVDD = 1.65V to 3.6V, unless otherwise noted. PARAMETER DESCRIPTION MIN MAX UNITS 2 16 1/fCLK SCLK pulse width, high and low (1) 0.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, and fDATA = 1000SPS, unless otherwise noted. OUTPUT SPECTRUM 0 OUTPUT SPECTRUM 0 VIN = -0.5dBFS, 31.25Hz THD = -121.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, and fDATA = 1000SPS, unless otherwise noted. SNR AND THD vs TEMPERATURE NOISE AND THD vs VREF 125 -117 123 -119 122 -121 6 -105 5 -110 4 -115 THD: VIN = 31.25Hz, -0.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, and fDATA = 1000SPS, unless otherwise noted. POWER vs fCLK GAIN AND OFFSET vs TEMPERATURE 16 100 200 5 Units Power (mW) 12 10 8 6 4 100 75 Gain Error 0 50 -100 25 0 -200 Offset Normalized Offset (mV) Normalized Gain Error (ppm) 14 -25 -300 2 0 0 0.5 1.0 1.5 2.0 2.5 fCLK (MHz) 3.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com OVERVIEW The ADS1281 is a high-performance analog-to-digital converter (ADC) intended for energy exploration, seismic monitoring, chromatography, and other exacting applications. The converter provides 24- or 32-bit output data in data rates from 4000SPS to 250SPS. Figure 19 shows the block diagram of the ADS1281.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 The RESET input resets the register settings (Register mode) and also restarts the conversion process. The PWDN input sets the device into a micro-power state. Note that register settings are not retained in PWDN mode. Use the STANDBY command in its place if it is desired to retain register settings (the quiescent current in the Standby mode is slightly higher).
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com The modulator is optimized for input signals within a 4kHz passband. As Figure 21 shows, the noise shaping of the modulator results in a sharp increase in noise above 6kHz. The modulator has a chopped input structure that further reduces noise within the passband. The noise is moved out of the passband and appears at the chopping frequency (fCLK/512 = 8kHz). The component at 6.5kHz is the tone frequency, shifted out of band by a 20mV offset.
ADS1281 VIN (% of Full-Scale) www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 FILTR[1:0] = 00. Pins DR0/M0 and DR1/M1 then become the modulator data outputs and the PHS/MCLK becomes the modulator clock output. When not in the modulator mode, these pins are inputs and must not float. +100 (AINP - AINN) 0 -100 MFLAG Figure 23. Modulator Over-Range Flag Operation MODULATOR OUTPUT MODE The modulator digital stream output is available directly, bypassing and disabling the internal digital filter.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com Table 4. Digital Filter Selection, Pin Mode DIGITAL FILTER The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rate.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 The frequency domain transfer function of the sinc filter is shown in Equation 3. 0 -0.5 5 pN ´ f sin fMOD Gain (dB) ½H(f)½ = -1.0 p´f fMOD N sin -1.5 -2.0 (3) -2.5 where: N = decimation ratio (see Table 5) -3.0 0 0.05 The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has zero gain.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com As shown in Figure 29, the FIR frequency response provides a flat passband to 0.375 of the data rate (±0.003dB passband ripple). Figure 30 shows the transition from passband to stop band. back (or alias) into the passband and cause errors. Placing an anti-alias, low-pass filter in front of the ADS1281 inputs is recommended to limit possible out-of-band input signals. Often, a single RC filter is sufficient. 2.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 Minimum Phase Response The minimum phase filter provides a short delay from the arrival of an input signal to the output, but the relationship (phase) is not constant versus frequency, as shown in Figure 32. The filter phase is selected by the PHS bit (Register mode) or the PHS/MCLK pin (Pin mode); Table 7 shows additional information. Table 7.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com ANALOG INPUT CIRCUITRY (AINP, AINN) The ADS1281 measures the differential input signal VIN = (AINP – AINN) against the differential reference VREF = (VREFP – VREFN) using internal capacitors that are continuously charged and discharged. Figure 36 shows the simplified schematic of the ADC input circuitry; the right side of the figure illustrates the input circuitry with the capacitors and switches replaced by an equivalent circuit.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 The charging of the input sampling capacitors draws a transient current from the source driving the ADS1281 ADC inputs. The average value of this current can be used to calculate an effective impedance (REFF) where REFF = VIN/IAVERAGE. These impedances scale inversely with fMOD. For example, if fMOD is reduced by a factor of two, the impedances double. ESD diodes protect the analog inputs.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com PIN AND REGISTER MODES SYNCHRONIZATION (SYNC PIN AND SYNC COMMAND) The PINMODE input (pin 21) is used to set the control mode of the device: Pin mode or Register mode. In Pin mode (PINMODE = 1), control of the device is set by pins; there are no registers to program. In Register mode, control of the device is set by the configuration registers.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 PULSE-SYNC MODE In Pulse-sync mode, the ADS1281 stops and restarts the conversion process when a sync event occurs (by pin or command). When the sync event occurs, the device resets the internal memory; DRDY goes high, and after the digital filter has settled, new conversion data are available, as shown in Figure 38 and Table 11.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com RESET (RESET Pin and Reset Command) The ADS1281 may be reset in two ways: toggle the RESET pin low or send a Reset command. When using the RESET pin, take it low and hold for at least 2/fCLK to force a reset. The ADS1281 is held in reset until the pin is released. By command, RESET takes effect on the next rising edge of fCLK after the eighth rising edge of SCLK of the command.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 DVDD POWER SUPPLY Serial Clock (SCLK) The DVDD supply operates over the range of +1.65V to +3.6V. If DVDD is operated at less than 2.25V, connect the DVDD pin to the BYPAS pin. If DVDD is greater than or equal to 2.25V, do not connect DVDD to the BYPAS pin. Figure 43 shows this connection. The serial clock (SCLK) is an input that is used to clock data into (DIN) and out of (DOUT) the ADS1281.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com Data Ready (DRDY) DATA FORMAT DRDY is an output; when it transitions low, this transition indicates new conversion data are ready, as shown in Figure 45. When reading data by the continuous mode, the data must be read within four CLK periods before DRDY goes low again or the data are overwritten with new conversion data.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 READING DATA The ADS1281 has two ways to read conversion data: Read Data Continuous and Read Data By Command. Read Data Continuous In the Read Data Continuous mode, the conversion data are shifted out directly from the device without the need for sending a read command. This mode is the default mode at power-on. This mode is also enabled by the RDATAC command.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com Read Data By Command ONE-SHOT OPERATION The Read Data Continuous mode is stopped by the SDATAC command. In this mode, conversion data are read by command. In the Read Data By Command mode, a read data command must be sent to the device for each data conversion (as shown in Figure 48). When the read data command is received (on the eighth SCLK rising edge), data are available to read only when DRDY goes low (tDR).
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 Table 17. Offset Calibration Values OFFSET AND FULL-SCALE CALIBRATION REGISTERS The conversion data can be scaled for offset and gain before yielding the final output code. As shown in Figure 50, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the full-scale register (FSC).
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com CALIBRATION COMMANDS OFSCAL Command Calibration commands may be sent to the ADS1281 to calibrate the conversion data. The values of the offset and gain calibration registers are internally written to perform calibration. The appropriate input signals must be applied to the ADS1281 inputs before sending the commands.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 USER CALIBRATION System calibration of the ADS1281 can be performed without using the calibration commands. This procedure requires the calibration values to be externally calculated and then written to the calibration registers. The steps for this procedure are: 1. Set the OFSCAL[2:0] register = 0h and GANCAL[2:0] = 400000h. These values set the offset and gain registers to 0 and 1, respectively. 2.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com COMMANDS The commands listed in Table 21 control the operation of the ADS1281. Command operations are only possible in Register mode. Most commands are stand-alone (that is, 1 byte in length); the register reads and writes require a second command byte in addition to the actual data bytes. In Read Data Continuous mode, the ADS1281 places conversion data on the DOUT pin as SCLK is applied.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 WAKEUP: Wake-Up From Standby Mode SDATAC: Stop Read Data Continuous Description: This command is used to exit the standby mode. Upon sending the command, the time for the first data to be ready is illustrated in Figure 41 and Table 14. Sending this command during normal operation has no effect; for example, reading data by the Read Data Continuous method with DIN held low. Description: This command stops the Read Data Continuous mode.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com OFSCAL: Offset Calibration GANCAL: Gain Calibration Description: This command performs an offset calibration. The inputs to the converter (or the inputs to the external pre-amplifier) should be zeroed and allowed to stabilize before sending this command. The offset calibration register updates after this operation. See the Calibration Commands section for more details. Description: This command performs a gain calibration.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 REGISTER MAP The Register mode (PINMODE = 0) allows read and write access to the device registers. Collectively, the registers contain all the information needed to configure the device, such as data rate, filter selection, calibration, etc. The registers are accessed by the RREG and WREG commands. The registers can be accessed individually or as a block of registers by sending or receiving consecutive bytes.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com CONFIG0: CONFIGURATION REGISTER 0 (ADDRESS 01h) 7 6 5 4 3 2 1 0 SYNC 1 DR2 DR1 DR0 PHASE FILTR1 FILTR0 Reset value = 52h.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 HPF1 and HPF0 These two bytes (high-byte and low-byte, respectively) set the corner frequency of the HPF. HPF0: High-Pass Filter Corner Frequency, Low Byte (Address 03h) 7 6 5 4 3 2 1 0 HP07 HP06 HP05 HP04 HP03 HP02 HP01 HP00 Reset value = 32h. HPF1: High-Pass Filter Corner Frequency, High Byte (Address 04h) 7 6 5 4 3 2 1 0 HP15 HP14 HP13 HP12 HP11 HP10 HP09 HP08 Reset value = 03h.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com CONFIGURATION GUIDE The ADS1281 offers two modes of operation: Pin Control mode and Register Control mode. In Pin Control mode, the operation of the device is controlled by the pins; there are no registers to program. In Register Control mode, the registers are used to control device operation. After RESET or power-on, the registers can be configured using the following procedure: 1. Reset the SPI interface.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 APPLICATION INFORMATION The ADS1281 is a very high-resolution ADC. Optimal device performance requires giving special attention to the support circuitry and printed circuit board (PCB) design. Locate noisy digital components, such as microcontrollers and oscillators, in an area of the PCB away from the converter or front-end components.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com Figure 57 shows the digital connection to an FPGA (field programmable gate array) device. In this example, two ADS1281s are shown connected. The DRDY output from each ADS1281 can be used; however, when the devices are synchronized, the DRDY output from only one device is sufficient. A shared SCLK line between the devices is optional. For best performance, the FPGA and the ADS281s should operate from the same clock.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 APPENDIX Table 24.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com Table 24.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 Table 24.
ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 1+ 1-2 HPF Gain Error Factor = 2- www.ti.com cos wN + sin wN - 1 cos wN cos wN + sin wN - 1 cos wN (11) See the HPF Stage section for an example of how to use this equation. HPF Transfer Function -1 2-a 1-Z ´ HPF(Z) = -1 1 - bZ 2 (12) where b is calculated as shown in Equation 13: 2 1 + (1 - a) b= 2 (13) Table 25.
ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2009) to Revision D Page • Added footnote 8 to Electrical Characteristics table ............................................................................................................. 3 • Moved Equation 12 and Equation 13 to the Appendix from the HPF Stage section .............................
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS1281IPWR Package Package Pins Type Drawing TSSOP PW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1281IPWR TSSOP PW 24 2000 367.0 367.0 38.
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